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Precision Analog Microcontroller, 12-Bit Analog I/O, Large Memory, ARM7TDMI MCU with Enhanced IRQ Handler
ADuC7124
FEATURES
Analog input/output Multichannel, 12-bit, 1 MSPS ADC Up to 12 ADC channels Fully differential and single-ended modes 0 V to VREF analog input range 12-bit voltage output DACs 2 DAC outputs available On-chip voltage reference On-chip temperature sensor (3C) Voltage comparator Microcontroller ARM7TDMI core, 16-bit/32-bit RISC architecture JTAG port supports code download and debug Clocking options Trimmed on-chip oscillator (3%) External watch crystal External clock source up to 41.78 MHz 41.78 MHz PLL with programmable divider Memory 126 kB flash/EE memory, 32 kB SRAM In-circuit download, JTAG-based debug Software-triggered in-circuit reprogrammability Vectored interrupt controller for FIQ and IRQ 8 priority levels for each interrupt type Interrupt on edge or level external pin inputs On-chip peripherals 2x fully I2C compatible channels SPI (20 MBPS in master mode, 10 MBPS in slave mode) With 4-byte FIFO on input and output stages 2x UART channels With 16-byte FIFO on input and output stages Up to 30 GPIO port All GPIOs are 5 V tolerant 4x general-purpose timers Watchdog timer (WDT) and wake-up timer Programmable logic array (PLA) 16 PLA elements 16-bit, 6-channel PWM Power supply monitor Power Specified for 3 V operation Active mode: 11 mA at 5 MHz, 50 mA at 41.78 MHz Packages and temperature range Fully specified for -40C to +125C operation 64-lead LFCSP Tools Low cost QuickStart development system Full third-party support
APPLICATIONS
Industrial control and automation systems Smart sensors, precision instrumentation Base station systems, optical networking Patient monitoring
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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ADuC7124 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Detailed Block Diagram .............................................................. 3 Specifications..................................................................................... 4 Timing Specifications .................................................................. 8 Absolute Maximum Ratings .......................................................... 12 ESD Caution ................................................................................ 12 Pin Configuration and Function Descriptions ........................... 13 Typical Performance Characteristics ........................................... 16 Terminology .................................................................................... 19 ADC Specifications .................................................................... 19 DAC Specifications..................................................................... 19 Overview of the ARM7TDMI Core ............................................. 20 Thumb Mode (T)........................................................................ 20 Long Multiply (M) ...................................................................... 20 EmbeddedICE (I) ....................................................................... 20 Exceptions ................................................................................... 20 ARM Registers ............................................................................ 20 Interrupt Latency ........................................................................ 21 Memory Organization ................................................................... 22 Memory Access ........................................................................... 22 Flash/EE Memory ....................................................................... 22 SRAM ........................................................................................... 22 Memory Mapped Registers ....................................................... 22 ADC Circuit Overview .................................................................. 30 Transfer Function ....................................................................... 30 Typical Operation ....................................................................... 31 MMRs Interface .......................................................................... 31 Converter Operation .................................................................. 33 Driving the Analog Inputs ........................................................ 34 Calibration ................................................................................... 35 Temperature Sensor ................................................................... 35 Band Gap Reference ................................................................... 36 Nonvolatile Flash/EE Memory ..................................................... 37 Programming .............................................................................. 37 Flash/EE Memory Security ....................................................... 38 Flash/EE Control Interface ....................................................... 38 Execution Time from SRAM and Flash/EE............................ 41 Reset and Remap ........................................................................ 41 Other Analog Peripherals .............................................................. 44 DAC.............................................................................................. 44 Power Supply Monitor ............................................................... 45 Comparator ................................................................................. 46 Oscillator and PLL--Power Control ........................................ 47 Digital Peripheral ........................................................................... 51 General-Purpose Input/Output................................................ 51 Serial Port Mux ........................................................................... 53 UART Serial Interface ................................................................ 53 Serial Peripheral Interface ......................................................... 59 I2C ................................................................................................. 63 PWM General Overview ........................................................... 71 Programmable Logic Array (PLA)........................................... 74 Processor Reference Peripherals................................................... 77 Interrupt System ......................................................................... 77 IRQ ............................................................................................... 77 Fast Interrupt Request (FIQ) .................................................... 78 Vectored Interrupt Controller (VIC) ....................................... 79 Timers .......................................................................................... 84 Hardware Design Considerations ................................................ 90 Power Supplies ............................................................................ 90 Grounding and Board Layout Recommendations................. 91 Clock Oscillator .......................................................................... 91 Power-on Reset Operation ........................................................ 92 Outline Dimensions ....................................................................... 93 Ordering Guide .......................................................................... 93
REVISION HISTORY
7/10--Revision 0: Initial Version
Rev. 0 | Page 2 of 96
ADuC7124 GENERAL DESCRIPTION
The ADuC7124 is a fully integrated, 1 MSPS, 12-bit data acquisition system incorporating high performance multichannel ADCs, 16-bit/32-bit MCUs, and Flash/EE memory on a single chip. The ADC consists of up to 12 single-ended inputs. An additional two inputs are available but are multiplexed with the two DAC output pins. The ADC can operate in single-ended or differential input mode. The ADC input voltage range is 0 V to VREF. A low drift band gap reference, temperature sensor, and voltage comparator complete the ADC peripheral set. The DAC output range is programmable to one of three voltage ranges. The DAC outputs have an enhanced feature of being able to retain their output voltage during a watchdog or software reset sequence. The device operates from an on-chip oscillator and a PLL generating an internal high frequency clock of 41.78 MHz. This clock is routed through a programmable clock divider from which the MCU core clock operating frequency is generated. The microcontroller core is an ARM7TDMI(R), 16-bit/32-bit RISC machine, which offers up to 41 MIPS of peak performance. Thirty-two kilobytes of SRAM and 126 kB of nonvolatile Flash/EE memory are provided on-chip. The ARM7TDMI core views all memory and registers as a single linear array. The ADuC7124 contains an advanced interrupt controller. The vectored interrupt controller (VIC) allows every interrupt to be assigned a priority level. It also supports nested interrupts to a maximum level of eight per IRQ and FIQ. When IRQ and FIQ interrupt sources are combined, a total of 16 nested interrupt levels are supported. On-chip factory firmware supports in-circuit download via the UART serial interface port or the I2C port, while nonintrusive emulation is also supported via the JTAG interface. These features are incorporated into a low cost QuickStartTM development system supporting this MicroConverter(R) family. The part contains a 16-bit PWM with six output signals. For communication purposes, the part contains 2x I2C channels that can be individually configured for master or slave mode. An SPI interface supporting both master and slave modes is also provided. Thirdly, 2x UART channels are provided. Each UART contains a configurable 16-bit FIFO with receive and transmit buffers. The part operates from 2.7 V to 3.6 V and is specified over an industrial temperature range of -40C to +125C. When operating at 41.78 MHz, the power dissipation is typically 120 mW. The ADuC7124 is available in a 64-lead LFCSP package.
DETAILED BLOCK DIAGRAM
ADC0 MUX ADC12 TEMP SENSOR CMP0 CMP1 CMPOUT VREF OSC AND PLL PSM PLA BAND GAP REF 1MSPS 12-BIT ADC
ADuC7124
12-BIT DAC 12-BIT DAC
DAC0
DAC1
VECTORED INTERRUPT CONTROLLER ARM7TDMI-BASED MCU WITH ADDITIONAL PERIPHERALS 8k x 32 SRAM 63k x 16 FLASH/EEPROM SPI, 2xI2C, 2xUART GPIO PWM EXTERNAL MEMORY INTERFACE
09123-001
XCLKI XCLKO
RST
POR
4 GENERALPURPOSE TIMERS
JTAG
Figure 1.
Rev. 0 | Page 3 of 96
ADuC7124 SPECIFICATIONS
AVDD = IOVDD = 2.7 V to 3.6 V, VREF = 2.5 V internal reference, fCORE = 41.78 MHz, TA = -40C to +125C, unless otherwise noted. Table 1.
Parameter ADC CHANNEL SPECIFICATIONS ADC Power-Up Time DC Accuracy 1, 2 Resolution Integral Nonlinearity Differential Nonlinearity3, 4 DC Code Distribution ENDPOINT ERRORS5 Offset Error Offset Error Match Gain Error Gain Error Match DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise Channel-to-Channel Crosstalk Min Typ 5 12 0.6 1.0 0.5 +0.7/-0.6 1 1 1 4 1 69 -78 -75 -90 1.5 +1/-0.9 Max Unit s Bits LSB LSB LSB LSB LSB LSB LSB LSB LSB dB dB dB dB fIN = 10 kHz sine wave, fSAMPLE = 1 MSPS Includes distortion and noise components Test Conditions/Comments Eight acquisition clocks and fADC/2
2.5 V internal reference 1.0 V external reference 2.5 V internal reference 1.0 V external reference ADC input is a dc voltage.
2
Measured on adjacent channels. Input channels not being sampled have a 25 kHz sine wave connected to them.
ANALOG INPUT Input Voltage Ranges4 Differential Mode Single-Ended Mode Leakage Current Input Capacitance ON-CHIP VOLTAGE REFERENCE Output Voltage Accuracy Reference Temperature Coefficient Power Supply Rejection Ratio Output Impedance Internal VREF Power-On Time EXTERNAL REFERENCE INPUT Input Voltage Range DAC CHANNEL SPECIFICATIONS DC Accuracy7 Resolution Relative Accuracy Differential Nonlinearity Offset Error Gain Error8 Gain Error Mismatch
1 24 2.5
VCM6 VREF/2 0 to VREF 6
V V A pF V mV ppm/C dB ms V
During ADC acquisition 0.47 F from VREF to AGND TA = 25C
5 15 80 45 1 0.625 AVDD
TA = 25C
RL = 5 k, CL = 100 pF 12 2 1 17 1.2 0.1 Bits LSB LSB mV % %
Guaranteed monotonic 2.5 V internal reference % of full scale on DAC0
Rev. 0 | Page 4 of 96
ADuC7124
Parameter ANALOG OUTPUTS Output Voltage Range 0 Output Voltage Range 1 Output Voltage Range 2 Output Impedance
DAC IN OP AMP MODE DAC Output Buffer in Op Amp Mode Input Offset Voltage Input Offset Voltage Drift Input Offset Current Input Bias Current Gain Unity Gain Frequency CMRR Settling Time Output Slew Rate PSRR
Min
Typ 0 to DACREF 0 to 2.5 0 to DACVDD 0.5
Max
Unit V V V
Test Conditions/Comments DACREF range: DACGND to DACVDD
0.4 4 2 2.5 70 4.5 78 12 3.2 75
mV V/C nA nA dB MHz dB s V/s dB
5 k load RL = 5 k, CL = 100 pF RL = 5 k, CL = 100 pF RL = 5 k, CL = 100 pF
DAC AC CHARACTERISTICS Voltage Output Settling Time Digital-to-Analog Glitch Energy
10 10
s nV-sec
1 LSB change at major carry (where maximum number of bits simultaneously change in the DACxDAT register)
COMPARATOR Input Offset Voltage Input Bias Current Input Voltage Range Input Capacitance Hysteresis4, 6 Response Time TEMPERATURE SENSOR Voltage Output at 25C Voltage TC Accuracy JA Thermal Impedance 64-Lead LFCSP POWER SUPPLY MONITOR (PSM) IOVDD Trip Point Selection Power Supply Trip Point Accuracy POWER-ON RESET WATCHDOG TIMER (WDT) Timeout Period FLASH/EE MEMORY Endurance9 Data Retention10 DIGITAL INPUTS Logic 1 Input Current Logic 0 Input Current Input Capacitance
15 1 AGND 8.5 2 4 15 AVDD - 1.2
mV A V pF mV s
Hysteresis can be turned on or off via the CMPHYST bit in the CMPCON register. 100 mV overdrive and configured with CMPRES = 11
1.415 3.914 3
24
V mV/C C C/W V V % V 512 sec Cycles Years
A single point calibration is required.
2.79 3.07 2.5 2.41 0 10,000 20 0.2 -40 -80 5 1 -60 -120
Two selectable trip points Of the selected nominal trip point voltage
A A A pF
TJ = 85C All digital inputs excluding XCLKI and XCLKO VIH = VDD or VIH = 5 V VIL = 0 V; except TDI, TDO, and RTCK VIL = 0 V; TDI, TDO, and RTCK
Rev. 0 | Page 5 of 96
ADuC7124
Parameter LOGIC INPUTS3 VINL, Input Low Voltage VINH, Input High Voltage LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage11 CRYSTAL INPUTS XCLKI and XCLKO Logic Inputs, XCLKI Only VINL, Input Low Voltage VINH, Input High Voltage XCLKI Input Capacitance XCLKO Output Capacitance INTERNAL OSCILLATOR MCU CLOCK RATE4 From 32 kHz Internal Oscillator From 32 kHz External Crystal Using an External Clock START-UP TIME At Power-On From Pause/Nap Mode From Sleep Mode From Stop Mode PROGRAMMABLE LOGIC ARRAY (PLA) Pin Propagation Delay Element Propagation Delay POWER REQUIREMENTS12, 13 Power Supply Voltage Range AVDD to AGND and IOVDD to IOGND Analog Power Supply Currents AVDD Current DACVDD Current14 Digital Power Supply Current IOVDD Current in Normal Mode Min Typ Max 0.8 2.0 2.4 0.4 Unit V V V V All digital outputs excluding XCLKO ISOURCE = 1.6 mA ISINK = 1.6 mA Test Conditions/Comments All logic inputs excluding XCLKI
0.8 1.6 20 20 32.768 3 326 41.78 0.05 0.05 66 2.6 247 1.58 1.7 12 2.5 44 41.78
V V pF pF kHz % kHz MHz MHz MHz ms s s ms ms ns ns CD = 7 CD = 0 TA = 85C TA = 125C Core clock = 41.78 MHz CD = 0 CD = 7
From input pin to output pin
2.7 165 0.02
3.6
V A A ADC in idle mode
IOVDD Current in Pause Mode IOVDD Current in Sleep Mode Additional Power Supply Currents ADC DAC
8.7 12 34 20 110 600 1.26 0.7 315
12.5 17 50 30 680
mA mA mA mA A A mA mA A
Code executing from Flash/EE CD = 7 CD = 3 CD = 0 (41.78 MHz clock) CD = 0 (41.78 MHz clock) TA = 85C TA = 125C at 1 MSPS at 62.5 kSPS per DAC
Rev. 0 | Page 6 of 96
ADuC7124
Parameter ESD TESTS HBM Passed Up To FICDM Passed Up To
1 2 3
Min
Typ
Max 3 1.5
Unit kV kV
Test Conditions/Comments 2.5 V reference, TA = 25C
All ADC channel specifications are guaranteed during normal core operation. Apply to all ADC input channels. Measured using the factory-set default values in the ADC offset register (ADCOF) and gain coefficient register (ADCGN). 4 Not production tested but supported by design and/or characterization data on production release. 5 Measured using the factory-set default values in ADCOF and ADCGN with an external AD845 op amp as an input buffer stage as shown in Figure 36. Based on external ADC system components, the user may need to execute a system calibration to remove external endpoint errors and achieve these specifications (see the Calibration section). 6 The input signal can be centered on any dc common-mode voltage (VCM) as long as this value is within the ADC voltage input range specified. 7 DAC linearity is calculated using a reduced code range of 100 to 3995. 8 DAC gain error is calculated using a reduced code range of 100 to internal 2.5 V VREF. 9 Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at -40C, +25C, +85C, and +125C. 10 Retention lifetime equivalent at junction temperature (TJ) = 85C as per JEDEC Standard 22 Method A117. Retention lifetime derates with junction temperature. 11 Test carried out with a maximum of eight I/Os set to a low output level. 12 Power supply current consumption is measured in normal, pause, and sleep modes under the following conditions: normal mode with 3.6 V supply, pause mode with 3.6 V supply, and sleep mode with 3.6 V supply. 13 IOVDD power supply current increases typically by 2 mA during a Flash/EE erase cycle. 14 This current must be added to the AVDD current.
Rev. 0 | Page 7 of 96
ADuC7124
TIMING SPECIFICATIONS
I2C Timing
Table 2. I2C Timing in Fast Mode (400 kHz)
Parameter tL tH tSHD tDSU tDHD tRSU tPSU tBUF tR tF Description SCLK low pulse width SCLK high pulse width Start condition hold time Data setup time Data hold time Setup time for repeated start Stop condition setup time Bus-free time between a stop condition and a start condition Rise time for both SCLK and SDATA Fall time for both SCLK and SDATA Min 200 100 300 100 0 100 100 1.3 Slave Max Master Typ 1360 1140 740 400 800 300 300 200 Unit ns ns ns ns ns ns ns s ns ns
Table 3. I2C Timing in Standard Mode (100 kHz)
Parameter tL tH tSHD tDSU tDHD tRSU tPSU tBUF tR tF Description SCLK low pulse width SCLK high pulse width Start condition hold time Data setup time Data hold time Setup time for repeated start Stop condition setup time Bus-free time between a stop condition and a start condition Rise time for both SCLK and SDATA Fall time for both SCLK and SDATA
tBUF tR
SDATA (I/O) MSB LSB ACK MSB
Min 4.7 4.0 4.0 250 0 4.7 4.0 4.7
Slave Max
3.45
1 300
Unit s ns s ns s s s s s ns
tDSU tPSU tSHD
SCLK (I) P S 1 2-7
tDHD tH
8
tDSU tRSU
9
tF tDHD tR
1 S(R) REPEATED START
STOP START CONDITION CONDITION
Figure 2. I2C Compatible Interface Timing
Rev. 0 | Page 8 of 96
09123-029
tL
tF
ADuC7124
SPI Timing
Table 4. SPI Master Mode Timing (Phase Mode = 1)
Parameter tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF
1
Description SCLOCK low pulse width1 SCLOCK high pulse width1 Data output valid after SCLOCK edge Data input setup time before SCLOCK edge1 Data input hold time after SCLOCK edge1 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time
Min
Typ (SPIDIV + 1) x tUCLK (SPIDIV + 1) x tUCLK
Max
25 1 x tUCLK 2 x tUCLK 5 5 5 5 12.5 12.5 12.5 12.5
Unit ns ns ns ns ns ns ns ns ns
tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
SCLOCK (POLARITY = 0) SCLOCK (POLARITY = 1)
tSH tSL tSR tSF
tDAV
MOSI MSB
tDF
tDR
BIT 6 TO BIT 1 LSB
MISO
MSB IN
BIT 6 TO BIT 1
LSB IN
09123-030
tDSU tDHD
Figure 3. SPI Master Mode Timing (Phase Mode = 1)
Table 5. SPI Master Mode Timing (Phase Mode = 0)
Parameter tSL tSH tDAV tDOSU tDSU tDHD tDF tDR tSR tSF
1
Description SCLOCK low pulse width1 SCLOCK high pulse width1 Data output valid after SCLOCK edge Data output setup before SCLOCK edge Data input setup time before SCLOCK edge1 Data input hold time after SCLOCK edge1 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time
Min
Typ (SPIDIV + 1) x tUCLK (SPIDIV + 1) x tUCLK
Max
25 75 1 x tUCLK 2 x tUCLK 5 5 5 5 12.5 12.5 12.5 12.5
Unit ns ns ns ns ns ns ns ns ns ns
tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
Rev. 0 | Page 9 of 96
ADuC7124
SCLOCK (POLARITY = 0)
tSH tSL tSR
SCLOCK (POLARITY = 1)
tSF
tDOSU
MOSI MSB
tDAV tDF tDR
BIT 6 TO BIT 1 LSB
MISO
MSB IN
BIT 6 TO BIT 1
LSB IN
tDHD
Figure 4. SPI Master Mode Timing (Phase Mode = 0)
Table 6. SPI Slave Mode Timing (Phase Mode = 1)
Parameter tCS tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tSFS
1
Description CS to SCLOCK edge SCLOCK low pulse width SCLOCK high pulse width Data output valid after SCLOCK edge Data input setup time before SCLOCK edge1 Data input hold time after SCLOCK edge1 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time CS high after SCLOCK edge
Min 200
Typ (SPIDIV + 1) x tHCLK (SPIDIV + 1) x tHCLK
Max
09123-031
tDSU
Unit ns ns ns ns ns ns ns ns ns ns ns
25 1 x tUCLK 2 x tUCLK 5 5 5 5 0 12.5 12.5 12.5 12.5
tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
CS
tCS
SCLOCK (POLARITY = 0)
tSFS
tSH tSL
tSR
SCLOCK (POLARITY = 1)
tSF
tDAV
MISO MSB
tDF
tDR
BIT 6 TO BIT 1 LSB
MOSI
MSB IN
BIT 6 TO BIT 1
LSB IN
09123-132
tDSU tDHD
Figure 5. SPI Slave Mode Timing (Phase Mode = 1)
Rev. 0 | Page 10 of 96
ADuC7124
Table 7. SPI Slave Mode Timing (Phase Mode = 0)
Parameter tCS tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tDOCS tSFS
1
Description CS to SCLOCK edge SCLOCK low pulse width SCLOCK high pulse width Data output valid after SCLOCK edge Data input setup time before SCLOCK edge1 Data input hold time after SCLOCK edge1 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time Data output valid after CS edge CS high after SCLOCK edge
Min 200
Typ (SPIDIV + 1) x tHCLK (SPIDIV + 1) x tHCLK
Max
Unit ns ns ns ns ns ns ns ns ns ns ns ns
25 1 x tUCLK 2 x tUCLK 5 5 5 5 0 12.5 12.5 12.5 12.5 25
tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
CS
tCS
SCLOCK (POLARITY = 0)
tSFS
tSH
SCLOCK (POLARITY = 1)
tSL tSR tSF
tDAV tDOCS tDF
MISO MSB
tDR
BIT 6 TO BIT 1 LSB
MOSI
MSB IN
BIT 6 TO BIT 1
LSB IN
09123-033
tDSU
tDHD
Figure 6. SPI Slave Mode Timing (Phase Mode = 0)
Rev. 0 | Page 11 of 96
ADuC7124 ABSOLUTE MAXIMUM RATINGS
AGND = REFGND = DACGND = GNDREF, TA = 25C, unless otherwise noted. Table 8.
Parameter AVDD to IOVDD AGND to DGND IOVDD to IOGND, AVDD to AGND Digital Input Voltage to IOGND Digital Output Voltage to IOGND VREF to AGND Analog Inputs to AGND Analog Outputs to AGND Operating Temperature Range, Industrial Storage Temperature Range Junction Temperature JA Thermal Impedance 64-Lead LFCSP Peak Solder Reflow Temperature SnPb Assemblies (10 sec to 30 sec) RoHS Compliant Assemblies (20 sec to 40 sec) Rating -0.3 V to +0.3 V -0.3 V to +0.3 V -0.3 V to +6 V -0.3 V to +5.3 V -0.3 V to IOVDD + 0.3 V -0.3 V to AVDD + 0.3 V -0.3 V to AVDD + 0.3 V -0.3 V to AVDD + 0.3 V -40C to +125C -65C to +150C 150C 24C/W 240C 260C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating can be applied at any one time.
ESD CAUTION
Rev. 0 | Page 12 of 96
ADuC7124 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADC3/CMP1 ADC2/CMP0 ADC1 ADC0 GNDREF AGND AVDD DACREF VREF RTCK P4.4/PLAO[12] P4.3/PLAO[11] P4.2/PLAO[10] P1.0/T1/SPM0/PLAI[0]/SIN0 P1.1/SPM1/PLAI[1]/SOUT0 P1.2/SPM2/PLAI[2] 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADCNEG DACGND DACV DD DAC0/ADC12 DAC1/ADC13 TMS TDI XCLKO XCLKI BM/P0.0/CMPOUT/PLAI[7]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
PIN 1 INDICATOR
ADuC7124
TOP VIEW (Not to Scale)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P1.3/SPM3/PLAI[3] P1.4/SPM4/PLAI[4]/IRQ2 P1.5/SPM5/PLAI[5]/IRQ3 P4.1/PLAO[9]/SOUT1 P4.0/PLAO[8]/SIN1 P1.6/SPM6/PLAI[6] P1.7/SPM7/PLAO[0] P3.7/PWMSYNC /PLAI[15] P3.6/PWMTRIP/PLAI[14] IOVDD IOGND P0.7/ECLK/XCLK/SPM8/PLAO[4]/SIN0 P2.0/SPM9/PLAO[5]/CONVSTART /SOUT0 IRQ1/P0.5/ADCBUSY /PLAO[2] IRQ0/P0.4/PWMTRIP/PLAO[1] RST
NC = NO CONNECT
Figure 7. Pin Configuration
Table 9. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Mnemonic ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADCNEG DACGND DACVDD DAC0/ADC12 DAC1/ADC13 TMS TDI XCLKO XCLKI Description Single-Ended or Differential Analog Input 4. Single-Ended or Differential Analog Input 5. Single-Ended or Differential Analog Input 6. Single-Ended or Differential Analog Input 7. Single-Ended or Differential Analog Input 8. Single-Ended or Differential Analog Input 9. Bias Point or Negative Analog Input of the ADC in Pseudo Differential Mode. Must be connected to the ground of the signal to convert. This bias point must be between 0 V and 1 V. Ground for the DAC. Typically connected to AGND. 3.3 V Power Supply for the DACs. Must be connected to AVDD. DAC0 Voltage Output/Single-Ended or Differential Analog Input 12. DAC1 Voltage Output/Single-Ended or Differential Analog Input 13. JTAG Test Port Input, Test Mode Select. Debug and download access. JTAG Test Port Input, Test Data In. Output from the Crystal Oscillator Inverter. Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator Circuits.
Rev. 0 | Page 13 of 96
09123-107
NOTES 1. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB GROUND TO ENSURE PROPER HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS.
DGND LVDD IOVDD IOGND P4.6/PLAO[14] P4.7/PLAO[15] P0.6/T1/MRST/PLAO[3] TCK TDO P3.0/PWM0/PLAI[8] P3.1/PWM1/PLAI[9] P3.2/PWM2/PLAI[10] P3.3/PWM3/PLAI[11] P0.3/TRST/ADCBUSY P3.4/PWM4/PLAI[12] P3.5/PWM5/PLAI[13]
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
ADuC7124
Pin No. 16 Mnemonic BM/P0.0/CMPOUT/PLAI[7] Description Multifunction I/O Pin. Boot mode. The ADuC7124 enters download mode if BM is low at reset and executes code if BM is pulled high at reset through a 1 k resistor. General-Purpose Input and Output Port 0.0/Voltage Comparator Output/Programmable Logic Array Input Element 7. Ground for Core Logic. 2.6 V Output of the On-Chip Voltage Regulator. This output must be connected to a 0.47 F capacitor to DGND only. 3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator. Ground for GPIO. Typically connected to DGND. General-Purpose Input and Output Port 4.6/Programmable Logic Array Output Element 14. General-Purpose Input and Output Port 4.7/Programmable Logic Array Output Element 15. Multifunction Pin, Driven Low After Reset. General-Purpose Output Port 0.6/Timer1 Input/Power-On Reset Output/Programmable Logic Array Output Element 3. JTAG Test Port Input, Test Clock. Debug and download access. JTAG Test Port Output, Test Data Out. General-Purpose Input and Output Port 3.0/PWM Phase 0/Output/Programmable Logic Array Input Element 8. General-Purpose Input and Output Port 3.1/PWM Phase 1/Programmable Logic Array Input Element 9. General-Purpose Input and Output Port 3.2/PWM Phase 2/Programmable Logic Array Input Element 10. General-Purpose Input and Output Port 3.3/PWM Phase 3/Programmable Logic Array Input Element 11. General-Purpose Input and Output Port 0.3/JTAG Test Port Input, Test Reset/ADCBUSY Signal Output. JTAG Reset input. Debug and download access. If this pin is held low, JTAG access is not possible because the JTAG interface is held in reset and P0.1/P0.2/P0.3 are configured as GPIO pins. General-Purpose Input and Output Port 3.4/PWM Phase 4/Programmable Logic Array Input 12. General-Purpose Input and Output Port 3.5/PWM Phase 5/Programmable Logic Array Input Element 13. Reset Input, Active Low. Multifunction I/O Pin. External Interrupt Request 0, Active High/General-Purpose Input and Output Port 0.4/PWM Trip External Input/Programmable Logic Array Output Element 1. Multifunction I/O Pin. External Interrupt Request 1, Active High/General-Purpose Input and Output Port 0.5/ADCBUSY Signal Output/Programmable Logic Array Output Element 2. Serial Port Multiplexed. General-Purpose Input and Output Port 2.0/Programmable Logic Array Output Element 5/Start Conversion Input Signal for ADC/UART0 Output. Serial Port Multiplexed. General-Purpose Input and Output Port 0.7/Output for External Clock Signal/Input to the Internal Clock Generator Circuits/Programmable Logic Array Output Element 4/UART0 Input. Ground for GPIO. Typically connected to DGND. 3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator. General-Purpose Input and Output Port 3.6/PWM Safety Cutoff/Programmable Logic Array Input Element 14. General-Purpose Input and Output Port 3.7/PWM Synchronization Input Output/Programmable Logic Array Input Element 15. Serial Port Multiplexed. General-Purpose Input and Output Port 1.7/UART, SPI/Programmable Logic Array Output Element 0. Serial Port Multiplexed. General-Purpose Input and Output Port 1.6/UART, SPI/Programmable Logic Array Input Element 6. General-Purpose Input and Output Port 4.0/Programmable Logic Array Output Element 8/UART1 Input.
Rev. 0 | Page 14 of 96
17 18 19 20 21 22 23
DGND LVDD IOVDD IOGND P4.6/PLAO[14] P4.7/PLAO[15] P0.6/T1/MRST/PLAO[3]
24 25 26 27 28 29 30
TCK TDO P3.0/PWM0/PLAI[8] P3.1/PWM1/PLAI[9] P3.2/PWM2/PLAI[10] P3.3/PWM3/PLAI[11] P0.3/TRST/ADCBUSY
31 32 33 34 35 36 37
P3.4/PWM4/PLAI[12] P3.5/PWM5/PLAI[13] RST IRQ0/P0.4/PWMTRIP/PLAO[1] IRQ1/P0.5/ADCBUSY/PLAO[2] P2.0/SPM9/PLAO[5]/CONVSTART/ SOUT0 P0.7/ECLK/XCLK/SPM8/PLAO[4]/SIN0
38 39 40 41 42
IOGND IOVDD P3.6/PWMTRIP/PLAI[14] P3.7/PWMSYNC/PLAI[15] P1.7/SPM7/PLAO[0]
43
P1.6/SPM6/PLAI[6]
44
P4.0/PLAO[8]/SIN1
ADuC7124
Pin No. 45 46 Mnemonic P4.1/PLAO[9]/SOUT1 P1.5/SPM5/PLAI[5]/IRQ3 Description General-Purpose Input and Output Port 4.1/Programmable Logic Array Output Element 9/UART1 Output. Serial Port Multiplexed. General-Purpose Input and Output Port 1.5/UART, SPI/Programmable Logic Array Input Element 5/External Interrupt Request 3, Active High. Serial Port Multiplexed. General-Purpose Input and Output Port 1.4/UART, SPI/Programmable Logic Array Input Element 4/External Interrupt Request 2, Active High. Serial Port Multiplexed. General-Purpose Input and Output Port 1.3/UART, I2C1/Programmable Logic Array Input Element 3. Serial Port Multiplexed. General-Purpose Input and Output Port 1.2/UART, I2C1/Programmable Logic Array Input Element 2. Serial Port Multiplexed. General-Purpose Input and Output Port 1.1/Timer1 Input/I2C0/Programmable Logic Array Input Element 1/UART0 Output. Serial Port Multiplexed. General-Purpose Input and Output Port 1.0/I2C0/Programmable Logic Array Input Element 0/UART0 Input. General-Purpose Input and Output Port 4.2/Programmable Logic Array Output Element 10. General-Purpose Input and Output Port 4.3/Programmable Logic Array Output Element 11. General-Purpose Input and Output Port 4.4/Programmable Logic Array Output Element 12. JTAG TEST port output, JTAG Return Test Clock. 2.5 V Internal Voltage Reference. Must be connected to a 0.47 F capacitor when using the internal reference. External Voltage Reference for the DACs. Range: DACGND to DACVDD. 3.3 V Analog Power. Analog Ground. Ground reference point for the analog circuitry. Ground Voltage Reference for the ADC. For optimal performance, the analog power supply should be separated from IOGND and DGND. Single-Ended or Differential Analog Input 0. Single-Ended or Differential Analog Input 1. Single-Ended or Differential Analog Input 2/Comparator Positive Input. Single-Ended or Differential Analog Input 3/Comparator Negative Input.
47
P1.4/SPM4/PLAI[4]/IRQ2
48
P1.3/SPM3/PLAI[3]
49
P1.2/SPM2/PLAI[2]
50
P1.1/SPM1/PLAI[1]/SOUT0
51
P1.0/T1/SPM0/PLAI[0]/SIN0
52 53 54 55 56 57 58 59 60 61 62 63 64
P4.2/PLAO[10] P4.3/PLAO[11] P4.4/PLAO[12] RTCK VREF DACREF AVDD AGND GNDREF ADC0 ADC1 ADC2/CMP0 ADC3/CMP1
Rev. 0 | Page 15 of 96
ADuC7124 TYPICAL PERFORMANCE CHARACTERISTICS
0.4
0.3
0.3
0.2
0.2
DNL (LSB)
0.1
DNL (LSB)
0.1
0
0
-0.1
09123-208
-0.1
09123-210
-0.2
-0.2
0
500
1500
2000
2500
3500
1000
3000
4000 4095
0
500
2000
1500
2500
3500
1000
ADC CODES
ADC CODES
Figure 8. Typical DNL Error, Temperature 25C, VREF = Internal 2.5 V, Single-Ended Mode ADCCP = ADC0, ADCCN = ADC0 Sampling Rate = 345 kHz Worst Case Positive = 0.38 LSB, Code 1567 Worst Case Negative= -0.24 LSB, Code 4094
0.6 0.5 0.4 0.3 0.2
Figure 10. Typical DNL Error, Temperature 25C, VREF = Internal 2.5 V, Single-Ended Mode ADCCP = ADC13/DAC1, ADCCN = ADC0 Sampling Rate = 345 kHz Worst Case Positive = 0.40 LSB, Code 607 Worst Case Negative= -0.27 LSB, Code 2486
0.6 0.5 0.4 0.3 0.2
INL (LSB)
0 -0.1 -0.2 -0.3 -0.4
09123-209
INL (LSB)
0.1
0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6
09123-211
-0.5 -0.6
0
500
1000
1500
2500
3000
2000
3500
4000 4095
0
500
1000
3000
3000
1500
2500
ADC CODES
ADC CODES
Figure 9. Typical INL Error, Temperature 25C, VREF = Internal 2.5 V, Single-Ended Mode ADCCP = ADC0, ADCCN = ADC0 Sampling Rate = 345 kHz Worst Case Positive = 0.60 LSB, Code 1890 Worst Case Negative= -0.54 LSB, Code 3485
Figure 11. Typical INL Error, Temperature 25C, VREF = Internal 2.5 V, Single-Ended Mode ADCCP = ADC13/DAC,1 ADCCN = ADC0 Sampling Rate = 345 kHz Worst Case Positive = 0.58 LSB, Code 480 Worst Case Negative= -0.54 LSB, Code 3614
Rev. 0 | Page 16 of 96
2000
3500
4000 4095
4000 4095
ADuC7124
0.4 0.3 0.2 0.4 0.3
0.2
DNL (LSB)
0.1 0 -0.1 -0.2 -0.3
DNL (LSB)
0.1
0
-0.1
09123-212 09123-214
-0.2
0
500
0
1500
2000
2500
3500
4000 4095
500
1500
2000
2500
3500
1000
3000
1000
ADC CODES
ADC CODES
Figure 12. Typical DNL Error, Temperature 25C, VREF = Internal 2.5 V, Single-Ended Mode ADCCP = ADC8, ADCCN = ADC0 Sampling Rate = 345 kHz Worst Case Positive = 0.42 LSB, Code 3583 Worst Case Negative= -0.32 LSB, Code 3073
0.8 0.6
Figure 14. Typical DNL Error, Temperature 25C, VREF = Internal 2.5 V, Single-Ended Mode ADCCP = ADC15/DAC3, ADCCN = ADC0 Sampling Rate = 345 kHz Worst Case Positive = 0.41 LSB, Code 2016 Worst Case Negative= -0.26 LSB, Code 3841
0.6 0.5 0.4
0.4 0.2
0.3 0.2
INL (LSB)
0 -0.2
INL (LSB)
0.1 0 -0.1 -0.2
-0.4
09123-213
-0.3 -0.4 -0.5 -0.6
09123-215
-0.6 -0.8
0
500
1000
3000
1500
2500
2000
3500
4000 4095
0
500
1000
3000
3000
1500
2500
ADC CODES
ADC CODES
Figure 13. Typical INL Error, Temperature 25C, VREF = Internal 2.5 V, Single-Ended Mode ADCCP = ADC8, ADCCN = ADC0 Sampling Rate = 345 kHz Worst Case Positive = 0.64 LSB, Code 802 Worst Case Negative= -0.69 LSB, Code 3485
Figure 15. Typical INL Error, Temperature 25C, VREF = Internal 2.5 V, Single-Ended Mode ADCCP = ADC15/DAC3, ADCCN = ADC0 Sampling Rate = 345 kHz Worst Case Positive = 0.55 LSB, Code 738 Worst Case Negative= -0.68 LSB, Code 3230
Rev. 0 | Page 17 of 96
2000
3500
4000 4095
4000 4095
ADuC7124
20 0 -20 -40 -60 -80 -100
09123-216
20 SNR: 69.85dB THD: -79.91dB PHSN: -82.93dB, 29.771kHz 0 -20 -40 -60 -80 -100
09123-219
SINAD, THD, AND PHSN OF ADC (dB)
-120 -140
SINAD, THD, AND PHSN OF ADC (dB)
SNR: 65.97dB THD: -78.63dB PHSN: -77.83dB, 146.6038kHz
-120 -140
0
50
100 FREQUENCY (kHz)
150
174.1
0
50
100 FREQUENCY (kHz)
150
174.1
Figure 16. SINAD, THD, and PHSN of ADC, VREF = Internal 2.5 V, Single-Ended Mode ADCCP = ADC0 ADCCN = ADC0
20 0 -20 -40 -60 -80 -100
09123-217
Figure 19. SINAD, THD, and PHSN of ADC, VREF = Internal 2.5V, Single-Ended Mode ADCCP = ADC15/DAC3 ADCCN = ADC0
0.2
DAC0 DAC1
SINAD, THD, AND PHSN OF ADC (dB)
SNR: 67.10dB THD: -79.79dB PHSN: -76.14dB, 54.9738kHz
0.1
DNL (LSB)
0
-0.1
09123-220
-120 -140
-0.2
250
500
750
1000
1250
1500
1750
2000
2250
2500
2750
3000
3250
3500
3750
FREQUENCY (kHz)
ADC CODES
Figure 17. SINAD, THD, and PHSN of ADC, VREF = Internal 2.5 V, Single-Ended Mode ADCCP = ADC13/DAC1 ADCCN = ADC0
20 0 -20 -40 SNR: 67.44dB THD: -82.33dB PHSN: -79.31dB, 54.9738kHz
Figure 20. DAC DNL Error, DAC0 Max Pos DNL: 0.188951 DAC1 Max Pos DNL:0.190343 DAC0 Max Neg DNL:-0.120081 DAC1 Max Neg DNL:-0.15697
2.0 1.5 1.0 0.5 DAC0 DAC1
SINAD, THD, AND PHSN OF ADC (dB)
INL (LSB)
0 -0.5 -1.0
-60 -80 -100
09123-218
-1.5 -2.0 -2.5
09123-221
-120 -140
250
500
750
1000
1250
1500
1750
2000
2250
2500
2750
3000
3250
3500
3750
FREQUENCY (kHz)
ADC CODES
Figure 18. SINAD, THD, and PHSN of ADC, VREF = Internal 2.5 V, Single-Ended Mode ADCCP = ADC8 ADCCN = ADC0
Figure 21. DAC INL Error, DAC0 Max Pos INL: 1.84106 DAC1 Max Pos INL:1.75312 DAC0 Max Neg INL: -0.887319: DAC1 Max Neg INL:-2.23708
Rev. 0 | Page 18 of 96
4000 4095
0
50
100
150
174.1
4000 4095
0
50
100
150
174.1
ADuC7124 TERMINOLOGY
ADC SPECIFICATIONS
Integral Nonlinearity (INL) The maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point 1/2 LSB below the first code transition, and full scale, a point 1/2 LSB above the last code transition. Differential Nonlinearity (DNL) The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Offset Error The deviation of the first code transition (0000 . . . 000) to (0000 . . . 001) from the ideal, that is, +1/2 LSB. Gain Error The deviation of the last code transition from the ideal AIN voltage (full scale - 1.5 LSB) after the offset error has been adjusted out. Signal to (Noise + Distortion) Ratio The measured ratio of signal to (noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Signal to (Noise + Distortion) = (6.02 N + 1.76) dB Thus, for a 12-bit converter, this is 74 dB. Total Harmonic Distortion The ratio of the rms sum of the harmonics to the fundamental.
DAC SPECIFICATIONS
Relative Accuracy Otherwise known as endpoint linearity, relative accuracy is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero error and full-scale error. Voltage Output Settling Time The amount of time it takes the output to settle to within a 1 LSB level for a full-scale input change.
Rev. 0 | Page 19 of 96
ADuC7124 OVERVIEW OF THE ARM7TDMI CORE
The ARM7(R) core is a 32-bit reduced instruction set computer (RISC). It uses a single 32-bit bus for instruction and data. The length of the data can be eight bits, 16 bits, or 32 bits. The length of the instruction word is 32 bits. The ARM7TDMI is an ARM7 core with four additional features. * * * * T support for the Thumb(R) (16-bit) instruction set. D support for debug. M support for long multiplications. I includes the EmbeddedICE module to support embedded system debugging.
EXCEPTIONS
ARM supports five types of exceptions and a privileged processing mode for each type. The five types of exceptions are * * Normal interrupt or IRQ. This is provided to service generalpurpose interrupt handling of internal and external events. Fast interrupt or FIQ. This is provided to service data transfers or communication channels with low latency. FIQ has priority over IRQ. Memory abort. Attempted execution of an undefined instruction. Software interrupt instruction (SWI). This can be used to make a call to an operating system.
THUMB MODE (T)
An ARM instruction is 32 bits long. The ARM7TDMI processor supports a second instruction set that has been compressed into 16 bits, called the Thumb instruction set. Faster execution from 16-bit memory and greater code density can usually be achieved by using the Thumb instruction set instead of the ARM instruction set, which makes the ARM7TDMI core particularly suitable for embedded applications. However, the Thumb mode has two limitations: * Thumb code typically requires more instructions for the same job. As a result, ARM code is usually best for maximizing the performance of time-critical code. The Thumb instruction set does not include some of the instructions needed for exception handling, which automatically switches the core to ARM code for exception handling.
* * *
Typically, the programmer defines interrupt as IRQ, but for higher priority interrupt, that is, faster response time, the programmer can define interrupt as FIQ.
ARM REGISTERS
ARM7TDMI has a total of 37 registers: 31 general-purpose registers and six status registers. Each operating mode has dedicated banked registers. When writing user-level programs, 15 general-purpose 32-bit registers (R0 to R14), the program counter (R15), and the current program status register (CPSR) are usable. The remaining registers are only used for system-level programming and exception handling. When an exception occurs, some of the standard registers are replaced with registers specific to the exception mode. All exception modes have replacement banked registers for the stack pointer (R13) and the link register (R14), as represented in Figure 22. The fast interrupt mode has more registers (R8 to R12) for fast interrupt processing. This means that the interrupt processing can begin without the need to save or restore these registers, and therefore, save critical time in the interrupt handling process.
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 (PC) SPSR_IRQ SPSR_UND R8_FIQ R9_FIQ R10_FIQ R11_FIQ R12_FIQ R13_FIQ R14_FIQ R13_SVC R14_SVC R13_ABT R14_ABT R13_IRQ R14_IRQ R13_UND R14_UND USABLE IN USER MODE SYSTEM MODES ONLY
*
See the ARM7TDMI user guide for details on the core architecture, the programming model, and both the ARM and ARM Thumb instruction sets.
LONG MULTIPLY (M)
The ARM7TDMI instruction set includes four extra instrucions that perform 32-bit by 32-bit multiplication with a 64-bit result and 32-bit by 32-bit multiplication-accumulation (MAC) with a 64-bit result. These results are achieved in fewer cycles than required on a standard ARM7 core.
EmbeddedICE (I)
EmbeddedICE provides integrated on-chip support for the core. The EmbeddedICE module contains the breakpoint and watchpoint registers that allow code to be halted for debugging purposes. These registers are controlled through the JTAG test port. When a breakpoint or watchpoint is encountered, the processor halts and enters debug state. Once in a debug state, the processor registers can be inspected as well as the Flash/EE, SRAM, and memory mapped registers.
CPSR
SPSR_FIQ FIQ MODE
SPSR_SVC SVC MODE
SPSR_ABT
USER MODE
ABORT MODE
IRQ MODE
UNDEFINED MODE
Figure 22. Register Organization
Rev. 0 | Page 20 of 96
09123-007
ADuC7124
More information relative to the model of the programmer and the ARM7TDMI core architecture can be found in the following materials from ARM: * * DDI0029G, ARM7TDMI Technical Reference Manual DDI-0100, ARM Architecture Reference Manual At the end of this time, the ARM7TDMI executes the instruction at 0x1C (FIQ interrupt vector address). The maximum total time is 50 processor cycles, which is just under 1.2 s in a system using a continuous 41.78 MHz processor clock. The maximum interrupt request (IRQ) latency calculation is similar but must allow for the fact that FIQ has higher priority and could delay entry into the IRQ handling routine for an arbitrary length of time. This time can be reduced to 42 cycles if the LDM command is not used. Some compilers have an option to compile without using this command. Another option is to run the part in Thumb mode where the time is reduced to 22 cycles. The minimum latency for FIQ or IRQ interrupts is a total of five cycles, which consist of the shortest time the request can take through the synchronizer plus the time to enter the exception mode. Note that the ARM7TDMI always runs in ARM (32-bit) mode when in privileged modes, for example, when executing interrupt service routines.
INTERRUPT LATENCY
The worst-case latency for a fast interrupt request (FIQ) consists of the following: * * The longest time the request can take to pass through the synchronizer The time for the longest instruction to complete (the longest instruction is an LDM) that loads all the registers including the PC The time for the data abort entry The time for the FIQ entry
* *
Rev. 0 | Page 21 of 96
ADuC7124 MEMORY ORGANIZATION
The ADuC7124 incorporates three separate blocks of memory: 32 kB of SRAM and two 64 kB blocks of on-chip Flash/EE memory. There are 126 kB of on-chip Flash/EE memory available to the user, and the remaining 2 kB are reserved for the system kernel. These blocks are mapped as shown in Figure 23. Note that, by default, after a reset, the Flash/EE memory is mirrored at Address 0x00000000. It is possible to remap the SRAM at Address 0x00000000 by clearing Bit 0 of the REMAP MMR. This remap function is described in more detail in the Flash/EE memory chapter.
0xFFFFFFFF MMRs 0xFFFF0000 RESERVED 0x0009F800 FLASH/EE 0x00080000 RESERVED 0x00047FFF SRAM 0x00040000 RESERVED 0x0001FFFF
09123-025
FLASH/EE MEMORY
The 128 kB of Flash/EE are organized as two banks of 32 kB x 16 bits. In the first block, 31 kB x 16 bits is user space and 1 kB x 16 bits is reserved for the factory-configured boot page. The page size of this Flash/EE memory is 512 bytes. The second 64 kB block is organized in a similar manner. It is arranged in 32 kB x 16 bits. All of this is available as user space. The 126 kB of Flash/EE are available to the user as code and non volatile data memory. There is no distinction between data and program because ARM code shares the same space. The real width of the Flash/EE memory is 16 bits, meaning that, in ARM mode (32-bit instruction), two accesses to the Flash/EE are necessary for each instruction fetch. Therefore, it is recommended that Thumb mode be used when executing from Flash/EE memory for optimum access speed. The maximum access speed for the Flash/EE memory is 41.78 MHz in Thumb mode and 20.89 MHz in full ARM mode (see the Execution Time from SRAM and Flash/EE section).
SRAM
The 32 kB of SRAM are available to the user, organized as 8 kB x 32 bits, that is, 16 kB words. ARM code can run directly from SRAM at 41.78 MHz, given that the SRAM array is configured as a 32-bit wide memory array (see the Execution Time from SRAM and Flash/EE section).
REMAPPABLE MEMORY SPACE (FLASH/EE OR SRAM) 0x00000000
Figure 23. Physical Memory Map
MEMORY ACCESS
The ARM7 core sees memory as a linear array of a 232 byte location where the different blocks of memory are mapped as outlined in Figure 23. The ADuC7124 memory organization is configured in little endian format: the least significant byte is located in the lowest byte address and the most significant byte in the highest byte address.
BIT 31 BYTE 3 . . . B 7 3 BYTE 2 . . . A 6 2 32 BITS BYTE 1 . . . 9 5 1 BIT 0 BYTE 0 . . . 8 4 0 0x00000004
09123-026
MEMORY MAPPED REGISTERS
The memory mapped register (MMR) space is mapped into the upper two pages of the memory array and accessed by indirect addressing through the ARM7 banked registers. The MMR space provides an interface between the CPU and all on-chip peripherals. All registers except the core registers reside in the MMR area. All shaded locations shown in Figure 25 are unoccupied or reserved locations and should not be accessed by user software. Table 28 shows a full MMR memory map. The access time reading or writing a MMR depends on the advanced microcontroller bus architecture (AMBA) bus used to access the peripheral. The processor has two AMBA buses: the advanced high performance bus (AHB) used for system modules, and the advanced peripheral bus (APB) used for the lower performance peripheral. Access to the AHB is one cycle, and access to the APB is two cycles. All peripherals on the ADuC7124 are on the APB except the Flash/EE memory and the GPIOs.
0xFFFFFFFF
0x00000000
Figure 24. Little Endian Format
Rev. 0 | Page 22 of 96
ADuC7124
0xFFFFFFFF
0xFFFFF880
FLASH CONTROL INTERFACE 1
0xFFFFF800
FLASH CONTROL INTERFACE 0
GPIO
0xFFFFF400
PWM
0xFFFF0F80
PLA
0xFFFF0B00
SPI
0xFFFF0A00
I2C1
0xFFFF0900
I2C0
0xFFFF0800
UART1
0xFFFF0740
UART0
0xFFFF0700
DAC
0xFFFF0600
ADC
0xFFFF0500
0xFFFF048C
BAND GAP REFERENCE
0xFFFF0440
POWER SUPPLY MONITOR
PLL AND OSCILLATOR CONTROL
0xFFFF0404
WATCHDOG TIMER
0xFFFF0360
WAKE-UP TIMER
0xFFFF0340
GENERAL-PURPOSE TIMER
0xFFFF0320
TIMER 0
0xFFFF0300
0xFFFF0220
REMAP AND SYSTEM CONTROL
09123-010
INTERRUPT CONTROLLER
0xFFFF0000
Figure 25. Memory Mapped Registers
Rev. 0 | Page 23 of 96
ADuC7124
Table 10. IRQ Base Address = 0xFFFF0000
Address 0xFFFF0000 0xFFFF0004 0xFFFF0008 0xFFFF000C 0xFFFF0010 0xFFFF0014 0xFFFF001C 0xFFFF0020 0xFFFF0024 0xFFFF0028 0xFFFF002C 0xFFFF0030 0xFFFF0034 0xFFFF0038 0xFFFF003C 0xFFFF0100 0xFFFF0104 0xFFFF0108 0xFFFF010C 0xFFFF011C 0xFFFF013C Name IRQSTA IRQSIG IRQEN IRQCLR SWICFG IRQBASE IRQVEC IRQP0 IRQP1 IRQP2 IRQP3 IRQCONN IRQCONE IRQCLRE IRQSTAN FIQSTA FIQSIG FIQEN FIQCLR FIQVEC FIQSTAN Byte 4 4 4 4 4 4 4 4 4 4 4 1 4 1 1 4 4 4 4 4 1 Access Type R R R/W W W R/W R R/W R/W R/W R/W R/W R/W W R/W R R R/W W R R/W
Table 11. System Control Base Address = 0xFFFF0200
Address 0xFFFF0220 0xFFFF0230 0xFFFF0234 0xFFFF0248 0xFFFF024C 0xFFFF0250 Address 0xFFFF0300 0xFFFF0304 0xFFFF0308 0xFFFF030C 0xFFFF0320 0xFFFF0324 0xFFFF0328 0xFFFF032C 0xFFFF0330 0xFFFF0340 0xFFFF0344 0xFFFF0348 0xFFFF034C 0xFFFF0360 0xFFFF0364 0xFFFF0368 0xFFFF036C Name REMAP RSTSTA RSTCLR RSTKEY0 RSTCFG RSTKEY1 Name T0LD T0VAL T0CON T0CLRI T1LD T1VAL T1CON T1CLRI T1CAP T2LD T2VAL T2CON T2CLRI T3LD T3VAL T3CON T3CLRI Byte 1 1 1 1 1 1 Byte 2 2 2 1 4 4 2 1 4 4 4 2 1 2 2 2 1 Access Type R/W R W W R/W W Access Type R/W R R/W W R/W R R/W W R/W R/W R R/W W R/W R R/W W
Table 12. Timer Base Address = 0xFFFF0300
Rev. 0 | Page 24 of 96
ADuC7124
Table 13. PLL/PSM Base Address = 0xFFFF0400
Address 0xFFFF0404 0xFFFF0408 0xFFFF040C 0xFFFF0410 0xFFFF0414 0xFFFF0418 0xFFFF0434 0xFFFF0438 0xFFFF043C Address 0xFFFF0440 0xFFFF0444 Address 0xFFFF048C Name POWKEY1 POWCON0 POWKEY2 PLLKEY1 PLLCON PLLKEY2 POWKEY3 POWCON1 POWKEY4 Name PSMCON CMPCON Name REFCON Byte 2 1 2 4 1 4 2 2 2 Byte 2 2 Byte 1 Access Type W R/W W W R/W W W R/W W Access Type R/W R/W Access Type R/W
Table 14. PSM Base Address = 0xFFFF0440
Table 15. Reference Base Address = 0xFFFF0480
Table 16. ADC Base Address = 0xFFFF0500
Address 0xFFFF0500 0xFFFF0504 0xFFFF0508 0xFFFF050C 0xFFFF0510 0xFFFF0514 0xFFFF0530 0xFFFF0534 0xFFFF0544 0xFFFF0548 Name ADCCON ADCCP ADCCN ADCSTA ADCDAT ADCRST ADCGN ADCOF TSCON TEMPREF Byte 2 1 1 1 4 1 2 2 1 2 Access Type R/W R/W R/W R R R/W R/W R/W R/W R/W
Table 17. DAC Address Base = 0xFFFF0600
Address 0xFFFF0600 0xFFFF0604 0xFFFF0608 0xFFFF060C 0xFFFF0654 Name DAC0CON DAC0DAT DAC1CON DAC1DAT DACBCFG Byte 1 4 1 4 1 Access Type R/W R/W R/W R/W R/W
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ADuC7124
Table 18. UART0 Base Address = 0xFFFF0700
Address 0xFFFF0700 0xFFFF0700 0xFFFF0700 0xFFFF0704 0xFFFF0704 0xFFFF0708 0xFFFF0708 0xFFFF070C 0xFFFF0710 0xFFFF0714 0xFFFF0718 0xFFFF072C Name COM0TX COM0RX COM0DIV0 COM0IEN0 COM0DIV1 COM0IID0 COM0FCR
COM0CON0 COM0CON1 COM0STA0 COM0STA1
COM0DIV2
Byte 1 1 1 1 1 1 1 1 1 2 2 2
Access Type R/W R R/W R/W R/W R R/W R/W R/W R R R/W
Cycle 2 2 2 2 2 2 2 2 2 2 2 2
Table 19. UART1 Base Address = 0xFFFF0740
Address 0xFFFF0740 0xFFFF0740 0xFFFF0740 0xFFFF0744 0xFFFF0744 0xFFFF0748 0xFFFF0748 0xFFFF074C 0xFFFF0750 0xFFFF0754 0xFFFF0758 0xFFFF076C Name COM1TX COM1RX COM1DIV0 COM1IEN0 COM1DIV1 COM1IID0 COM1FCR COM1CON0 COM1CON1 COM1STA0 COM1STA1 COM1DIV2 Byte 1 1 1 1 1 1 1 1 1 2 2 2 Access Type R/W R R/W R/W R/W R R/W R/W R/W R R R/W Cycle 2 2 2 2 2 2 2 2 2 2 2
Table 20. I2C0 Base Address = 0xFFFF0800
Address 0xFFFF0800 0xFFFF0804 0xFFFF0808 0xFFFF080C 0xFFFF0810 0xFFFF0814 0xFFFF0818 0xFFFF081C 0xFFFF0824 0xFFFF0828 0xFFFF082C 0xFFFF0830 0xFFFF0834 0xFFFF0838 0xFFFF083C 0xFFFF0840 0xFFFF0844 0xFFFF0848 0xFFFF084C Name I2C0MCON I2C0MSTA I2C0MRX I2C0MTX I2C0MRCNT I2C0MCRCNT I2C0ADR0 I2C0ADR1 I2C0DIV I2C0SCON I2C0SSTA I2C0SRX I2C0STX I2C0ALT I2C0ID0 I2C0ID1 I2C0ID2 I2C0ID3 I2C0FSTA Byte 2 2 1 2 2 1 1 1 2 2 2 1 1 1 1 1 1 1 1 Access Type R/W R R R/W R/W R R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Rev. 0 | Page 26 of 96
ADuC7124
Table 21. I2C1 Base Address = 0xFFFF0900
Address 0xFFFF0900 0xFFFF0904 0xFFFF0908 0xFFFF090C 0xFFFF0910 0xFFFF0914 0xFFFF0918 0xFFFF091C 0xFFFF0924 0xFFFF0928 0xFFFF092C 0xFFFF0930 0xFFFF0934 0xFFFF0938 0xFFFF093C 0xFFFF0940 0xFFFF0944 0xFFFF0948 0xFFFF094C Address 0xFFFF0A00 0xFFFF0A04 0xFFFF0A08 0xFFFF0A0C 0xFFFF0A10 Address 0xFFFF0B00 0xFFFF0B04 0xFFFF0B08 0xFFFF0B0C 0xFFFF0B10 0xFFFF0B14 0xFFFF0B18 0xFFFF0B1C 0xFFFF0B20 0xFFFF0B24 0xFFFF0B28 0xFFFF0B2C 0xFFFF0B30 0xFFFF0B34 0xFFFF0B38 0xFFFF0B3C 0xFFFF0B40 0xFFFF0B44 0xFFFF0B48 0xFFFF0B4C 0xFFFF0B50 0xFFFF0B54 Name I2C1MCON I2C1MSTA I2C1MRX I2C1MTX I2C1MRCNT0 I2C1MCRCNT I2C1ADR0 I2C1ADR1 I2C1DIV I2C1SCTL I2C1SSTA I2C1SRX I2C1STX I2C1ALT I2C1ID0 I2C1ID1 I2C1ID2 I2C1ID3 I2C1FSTA Name SPISTA SPIRX SPITX SPIDIV SPICON Name PLAELM0 PLAELM1 PLAELM2 PLAELM3 PLAELM4 PLAELM5 PLAELM6 PLAELM7 PLAELM8 PLAELM9 PLAELM10 PLAELM11 PLAELM12 PLAELM13 PLAELM14 PLAELM15 PLACLK PLAIRQ PLAADC PLADIN PLADOUT PLALCK Byte 2 2 1 2 2 1 1 1 2 2 2 1 1 1 1 1 1 1 1 Byte 2 1 1 1 2 Byte 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 4 4 4 1
Rev. 0 | Page 27 of 96
Access Type R/W R R R/W R/W R R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W Access Type R R W R/W R/W Access Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W
Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Cycle 2 2 2 2 2 Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Table 22. SPI Base Address = 0xFFFF0A00
Table 23. PLA Base Address = 0xFFFF0B00
ADuC7124
Table 24. GPIO Base Address = 0xFFFF0400
Address 0xFFFFF400 0xFFFFF404 0xFFFFF408 0xFFFFF40C 0xFFFFF410 0xFFFFF420 0xFFFFF424 0xFFFFF428 0xFFFFF42C 0xFFFFF430 0xFFFFF434 0xFFFFF438 0xFFFFF43C 0xFFFFF440 0xFFFFF444 0xFFFFF448 0xFFFFF48C 0xFFFFF450 0xFFFFF454 0xFFFFF458 0xFFFFF45C 0xFFFFF460 0xFFFFF464 0xFFFFF468 0xFFFFF46C Name GP0CON GP1CON GP2CON GP3CON GP4CON GP0DAT GP0SET GP0CLR GP0PAR GP1DAT GP1SET GP1CLR GP1PAR GP2DAT GP2SET GP2CLR GP2PAR GP3DAT GP3SET GP3CLR GP3PAR GP4DAT GP4SET GP4CLR GP4PAR Byte 4 4 4 4 4 4 1 1 4 4 1 1 4 4 1 1 4 4 1 1 4 4 1 1 4 Access Type R/W R/W R/W R/W R/W R/W W W R/W R/W W W R/W R/W W W R/W R/W W W R/W R/W W W R/W Cycle 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Table 25. Flash/EE Block 0 Base Address = 0xFFFFF800
Address 0xFFFFF800 0xFFFFF804 0xFFFFF808 0xFFFFF80C 0xFFFFF810 0xFFFFF818 0xFFFFF81C 0xFFFFF820 Name FEE0STA FEE0MOD FEE0CON FEE0DAT FEE0ADR FEE0SGN FEE0PRO FEE0HID Byte 1 1 1 2 2 3 4 4 Access Type R R/W R/W R/W R/W R R/W R/W Cycle 1 1 1 1 1 1 1 1
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ADuC7124
Table 26. Flash/EE Block 1 Base Address = 0xFFFFF880
Address 0xFFFFF880 0xFFFFF884 0xFFFFF888 0xFFFFF88C 0xFFFFF890 0xFFFFF898 0xFFFFF89C 0xFFFFF8A0 Name FEE1STA FEE1MOD FEE1CON FEE1DAT FEE1ADR FEE1SGN FEE1PRO FEE1HID Byte 1 1 1 2 2 3 4 4 Access Type R R/W R/W R/W R/W R R/W R/W Cycle 1 1 1 1 1 1 1 1
Table 27. PWM Base Address= 0xFFFF0F80
Address 0xFFFF0F80 0xFFFF0F84 0xFFFF0F88 0xFFFF0F8C 0xFFFF0F90 0xFFFF0F94 0xFFFF0F98 0xFFFF0F9C 0xFFFF0FA0 0xFFFF0FA4 0xFFFF0FA8 0xFFFF0FAC 0xFFFF0FB0 0xFFFF0FB4 0xFFFF0FB8 Name PWMCON1 PWM0COM0 PWM0COM1 PWM0COM2 PWM0LEN PWM1COM0 PWM1COM1 PWM1COM2 PWM1LEN PWM2COM0 PWM2COM1 PWM2COM2 PWM2LEN PWMCON2 PWMCLRI Byte 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Access Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Rev. 0 | Page 29 of 96
ADuC7124 ADC CIRCUIT OVERVIEW
The analog-to-digital converter (ADC) incorporates a fast, multichannel, 12-bit ADC. It can operate from 2.7 V to 3.6 V supplies and is capable of providing a throughput of up to 1 MSPS when the clock source is 41.78 MHz. This block provides the user with a multichannel multiplexer, a differential track-and-hold, an on-chip reference, and an ADC. The ADC consists of a 12-bit successive approximation converter based around two capacitor DACs. Depending on the input signal configuration, the ADC can operate in one of three different modes. * * * Fully differential mode, for small and balanced signals Single-ended mode, for any single-ended signals Pseudo differential mode, for any single-ended signals, taking advantage of the common-mode rejection offered by the pseudo differential input The ideal code transitions occur midway between successive integer LSB values (that is, 1/2 LSB, 32 LSB, 52 LSB, ... , FS - 3/2 LSB). The ideal input/output transfer characteristic is shown in Figure 27.
1111 1111 1111 1111 1111 1110 1111 1111 1101
OUTPUT CODE
1111 1111 1100 1LSB =
FULLSCALE 4096
0000 0000 0011 0000 0000 0010 0000 0000 0001 0V 1LSB VOLTAGE INPUT +FS - 1LSB
09123-012
09123-013
0000 0000 0000
The converter accepts an analog input range of 0 V to VREF when operating in single-ended or pseudo differential mode. In fully differential mode, the input signal must be balanced around a common-mode voltage (VCM) in the 0 V to AVDD range with a maximum amplitude of 2 x VREF (see Figure 26).
AVDD VCM VCM 2VREF 2VREF
Figure 27. ADC Transfer Function in Pseudo Differential or Single-Ended Mode
Fully Differential Mode
The amplitude of the differential signal is the difference between the signals applied to the VIN+ and VIN- pins (that is, VIN+ - VIN-). VIN+ is selected by the ADCCP register, and VIN- is selected by the ADCCN register. The maximum amplitude of the differential signal is, therefore, -VREF to +VREF p-p (that is, 2 x VREF). This is regardless of the common mode (CM). The common mode is the average of the two signals, for example, (VIN+ + VIN-)/2, and is, therefore, the voltage that the two inputs are centered on. This results in the span of each input being CM VREF/2. This voltage has to be set up externally, and its range varies with VREF (see the Driving the Analog Inputs section). The output coding is twos complement in fully differential mode with 1 LSB = 2 x VREF/4096, or 2 x 2.5 V/4096 = 1.22 mV when VREF = 2.5 V. The output result is 11 bits, but this is shifted by one to the right. This allows the result in ADCDAT to be declared as a signed integer when writing C code. The designed code transitions occur midway between successive integer LSB values (that is, 1/2 LSB, 32 LSB, 52 LSB, ... , FS - 32 LSB). The ideal input/output transfer characteristic is shown in Figure 28.
SIGN BIT 0 1111 1111 1110 0 1111 1111 1100 0 1111 1111 1010 1LSB = 2 x VREF 4096
0
Figure 26. Examples of Balanced Signals in Fully Differential Mode
A high precision, low drift, factory calibrated, 2.5 V reference is provided on chip. An external reference can also be connected as described in the Band Gap Reference section. Single or continuous conversion modes can be initiated in the software. An external CONVSTART pin, an output generated from the on-chip PLA, or a Timer0 or Timer1 overflow can also be used to generate a repetitive trigger for ADC conversions. A voltage output from an on-chip band gap reference proportional to absolute temperature can also be routed through the front-end ADC multiplexer, effectively an additional ADC channel input. This facilitates an internal temperature sensor channel that measures die temperature.
09123-011
VCM
2VREF
TRANSFER FUNCTION
Pseudo Differential and Single-Ended Modes
In pseudo differential or single-ended mode, the input range is 0 V to VREF. The output coding is straight binary in pseudo differential and single-ended modes with 1 LSB = FS/4096, or 2.5 V/4096 = 0.61 mV, or 610 V when VREF = 2.5 V
OUTPUT CODE
0 0000 0000 0010 0 0000 0000 0000 1 1111 1111 1110
1 0000 0000 0100 1 0000 0000 0010 1 0000 0000 0000 0LSB +VREF - 1LSB -VREF + 1LSB VOLTAGE INPUT (VIN+ - VIN-)
Figure 28. ADC Transfer Function in Differential Mode
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ADuC7124
TYPICAL OPERATION
Once configured via the ADC control and channel selection registers, the ADC converts the analog input and provides a 12-bit result in the ADC data register. The top four bits are the sign bits. The 12-bit result is placed in Bit 16 to Bit 27 as shown in Figure 29. Again, it should be noted that in fully differential mode, the result is represented in twos complement format. In pseudo differential and single-ended modes, the result is represented in straight binary format.
31 27 16 15 0
09123-014
ADCCON Register
Name: Address: Default Value: Access: ADCCON 0xFFFF0500 0x0600 Read/write
SIGN BITS
12-BIT ADC RESULT
ADCCON is an ADC control register that allows the programmer to enable the ADC peripheral, select the mode of operation of the ADC (either in single-ended mode, pseudo differential mode, or fully differential mode), and select the conversion type. This MMR is described in Table 28. Table 28. ADCCON MMR Bit Designations
Bit 15:14 13 Value Description Reserved. Set by the user to enable edge trigger mode. Cleared by the user to enable level trigger mode. ADC clock speed. fADC/1. This divider is provided to obtain 1 MSPS ADC with an external clock <41.78 MHz. fADC/2 (default value). fADC/4. fADC/8. fADC/16. fADC/32. ADC acquisition time. Two clocks. Four clocks. Eight clocks (default value). 16 clocks. Enable start conversion. Set by the user to start any type of conversion command. Cleared by the user to disable a start conversion (clearing this bit does not stop the ADC when continuously converting). Enable ADCBUSY. Set by the user to enable the ADCBUSY pin. Cleared by the user to disable the ADCBUSY pin. ADC power control. Set by the user to place the ADC in normal mode (the ADC must be powered up for at least 5 s before it converts correctly). Cleared by the user to place the ADC in powerdown mode. Conversion mode. Single-ended mode. Differential mode. Pseudo differential mode. Reserved.
Figure 29. ADC Result Format
The same format is used in DACxDAT, simplifying the software.
Current Consumption
The ADC in standby mode, that is, powered up but not converting, typically consumes 640 A. The internal reference adds 140 A. During conversion, the extra current is 0.3 A multiplied by the sampling frequency (in kHz).
12:10 000 001 010 011 100 101 9:8 00 01 10 11 7
Timing
Figure 30 gives details of the ADC timing. The user controls the ADC clock speed and the number of acquisition clocks in the ADCCON MMR. By default, the acquisition time is eight clocks, and the clock divider is two. The number of extra clocks (such as bit trial or write) is set to 19, which gives a sampling rate of 774 kSPS. For conversion on temperature sensor, the ADC acquisition time is automatically set to 16 clocks, and the ADC clock divider is set to 32. When using multiple channels including the temperature sensor, the timing settings revert to the user-defined settings after reading the temperature sensor channel.
ACQ BIT TRIAL WRITE
ADC CLOCK
CONVSTART
6
ADCBUSY
5
ADCDAT DATA
ADCSTA = 0
ADCSTA = 1 ADC INTERRUPT
09123-015
Figure 30. ADC Timing
4:3 00 01 10 11
MMRS INTERFACE
The ADC is controlled and configured via the eight MMRs.
Rev. 0 | Page 31 of 96
ADuC7124
Bit 2:0 Value 000 001 010 011 Description Conversion type. Enable CONVSTART pin as a conversion input. Enable Timer1 as a conversion input. Enable Timer0 as a conversion input. Single software conversion. Sets to 000 after conversion (note that Bit 7 of ADCCON MMR should be cleared after starting a single software conversion to avoid further conversions triggered by the CONVSTART pin). Continuous software conversion. PLA conversion. Reserved.
ADCCN Register
Name: Address: Default Value: Access: ADCCN 0xFFFF0508 0x01 Read/write
100 101 Other
ADCCN is an ADC negative channel selection register. This MMR is described in Table 30. Table 30. ADCCN MMR Bit Designation
Bit 7:5 4:0 Value Description Reserved. Negative channel selection bits. ADC0. ADC1. ADC2. ADC3. ADC4. ADC5. ADC6. ADC7. ADC8. ADC9. ADC10. ADC11. ADC12/DAC0. ADC13/DAC1. ADC14/DAC2. ADC15/DAC3. Reserved. AGND. Reserved. Reserved. Reserved.
ADCCP Register
Name: Address: Default Value: Access: ADCCP 0xFFFF0504 0x00 Read/write
ADCCP is an ADC positive channel selection register. This MMR is described in Table 29. Table 29. ADCCP1 MMR Bit Designation
Bit 7:5 4:0 Value Description Reserved. Positive channel selection bits. ADC0. ADC1. ADC2. ADC3. ADC4. ADC5. ADC6. ADC7. ADC8. ADC9. ADC10. ADC11. ADC12/DAC0. ADC13/DAC1. ADC14/DAC2. ADC15/DAC3. Temperature sensor. AGND (self-diagnostic feature). Internal reference (self-diagnostic feature). AVDD/2. Reserved.
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 Others
1
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 Others
ADCSTA Register
Name: Address: Default Value: Access: ADCSTA 0xFFFF050C 0x00 Read only
ADC and DAC channel availability depends on part model. See the Ordering Guide for details.
ADCSTA is an ADC status register that indicates when an ADC conversion result is ready. The ADCSTA register contains only one bit, ADCReady (Bit 0), representing the status of the ADC. This bit is set at the end of an ADC conversion, generating an ADC interrupt. It is cleared automatically by reading the ADCDAT MMR. When the ADC is performing a conversion, the status of the ADC can be read externally via the ADCBUSY pin. This pin is high during a conversion. When the conversion is finished, ADCBUSY goes back low. This information is available
Rev. 0 | Page 32 of 96
ADuC7124
on P0.5 (see the General-Purpose Input/Output section) if enabled in the ADCCON register. comparator is held in a balanced condition, and the sampling capacitor arrays acquire the differential signal on the input.
CAPACITIVE DAC AIN0 MUX CHANNEL+ B A SW1 CHANNEL- A SW2 B CAPACITIVE DAC
09123-017 09123-019 09123-018
ADCDAT Register
Name: Address: Default Value: Access: ADCDAT 0xFFFF0510 0x00000000 Read only
CS COMPARATOR
CS
SW3
CONTROL LOGIC
AIN11
VREF
ADCDAT is an ADC data result register that holds the 12-bit ADC resulst, as shown in Figure 29.
Figure 31. ADC Acquisition Phase
ADCRST Register
Name: Address: Default Value: Access: ADCRST 0xFFFF0514 0x00 Read/write
ADCRST resets the digital interface of the ADC. Writing any value to this register resets all the ADC registers to their default values.
ADCGN Register
Name: Address: Default Value: Access: ADCGN 0xFFFF0530 0x0200 Read/write
When the ADC starts a conversion, as shown in Figure 32, SW3 opens, and then SW1 and SW2 move to Position B. This causes the comparator to become unbalanced. Both inputs are disconnected once the conversion begins. The control logic and the charge redistribution DACs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC output code. The output impedances of the sources driving the VIN+ and VIN- pins must be matched; otherwise, the two inputs have different settling times, resulting in errors.
CAPACITIVE DAC AIN0 MUX AIN11 CHANNEL- A SW2 B CHANNEL+ B A SW1 CS SW3 CS COMPARATOR
CONTROL LOGIC
ADCGN is a 10-bit gain calibration register.
VREF
ADCOF Register
Name: Address: Default Value: Access: ADCOF 0xFFFF0534 0x0200 Read/write
Figure 32. ADC Conversion Phase
CAPACITIVE DAC
Pseudo Differential Mode
In pseudo differential mode, Channel- is linked to the ADCNEG pin of the ADuC7124. In Figure 33, ADCNEG is represented as VIN-. SW2 switches between A (Channel-) and B (VREF). The ADCNEG pin must be connected to ground or to a low voltage. The input signal on VIN+ can then vary from VIN- to VREF + VIN-. Note that VIN- must be chosen so that VREF + VIN- do not exceed AVDD.
CAPACITIVE DAC AIN0 MUX AIN11 A B VIN- VREF CHANNEL- CAPACITIVE DAC SW2 CHANNEL+ B A SW1 CS SW3 CS COMPARATOR
ADCOF is a 10-bit offset calibration register.
CONVERTER OPERATION
The ADC incorporates a successive approximation (SAR) architecture involving a charge-sampled input stage. This architecture can operate in three different modes: differential, pseudo differential, and single-ended.
Differential Mode
The ADuC7124 contains a successive approximation ADC based on two capacitive DACs. Figure 31 and Figure 32 show simplified schematics of the ADC in acquisition and conversion phases, respectively. The ADC comprises control logic, a SAR, and two capacitive DACs. In Figure 31 (the acquisition phase), SW3 is closed and SW1 and SW2 are in Position A. The
CONTROL LOGIC
Figure 33. ADC in Pseudo Differential Mode
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ADuC7124
Single-Ended Mode
In single-ended mode, SW2 is always connected internally to ground. The VIN- pin can be floating. The input signal range on VIN+ is 0 V to VREF.
CAPACITIVE DAC AIN0 MUX AIN11 CHANNEL- CHANNEL+ B A SW1 CS SW3 CS COMPARATOR
CONTROL LOGIC
For ac applications, removing high frequency components from the analog input signal is recommended by using an RC lowpass filter on the relevant analog input pins. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances significantly affect the ac performance of the ADC. This can necessitate the use of an input buffer amplifier. The choice of the op amp is a function of the particular application. Figure 36 and Figure 37 give an example of the ADC front end.
ADuC7124
10 ADC0 0.01F
09123-061
CAPACITIVE DAC
Figure 34. ADC in Single-Ended Mode
Analog Input Structure
Figure 35 shows the equivalent circuit of the analog input structure of the ADC. The four diodes provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300 mV; this can cause these diodes to become forward-biased and start conducting into the substrate. These diodes can conduct up to 10 mA without causing irreversible damage to the part. The C1 capacitors in Figure 35 are typically 4 pF and can be primarily attributed to pin capacitance. The resistors are lumped components made up of the on resistance of the switches. The value of these resistors is typically about 100 . The C2 capacitors are the sampling capacitors of the ADC and typically have a capacitance of 16 pF.
AVDD D
09123-020
Figure 36. Buffering Single-Ended/Pseudo Differential Input
ADuC7124
ADC0 VREF
09123-062
ADC1
Figure 37. Buffering Differential Inputs
When no amplifier is used to drive the analog input, the source impedance should be limited to values lower than 1 k. The maximum source impedance depends on the amount of total harmonic distortion (THD) that can be tolerated. The THD increases as the source impedance increases and the performance degrades.
DRIVING THE ANALOG INPUTS
R1 C2
C1
D
AVDD D
R1 C2
Internal or external references can be used for the ADC. In differential mode of operation, there are restrictions on the common-mode input signal (VCM), which is dependent upon the reference value and supply voltage used to ensure that the signal remains within the supply rails. Table 31 gives some calculated VCM minimum and VCM maximum values.
C1
D
09123-021
Figure 35. Equivalent Analog Input Circuit Conversion Phase: Switches Open, Track Phase: Switches Closed
Table 31. VCM Ranges
AVDD 3.3 V VREF 2.5 V 2.048 V 1.25 V 2.5 V 2.048 V 1.25 V VCM Min 1.25 V 1.024 V 0.75 V 1.25 V 1.024 V 0.75 V VCM Max 2.05 V 2.276 V 2.55 V 1.75 V 1.976 V 2.25 V Signal Peak-to-Peak 2.5 V 2.048 V 1.25 V 2.5 V 2.048 V 1.25 V
3.0 V
Rev. 0 | Page 34 of 96
ADuC7124
CALIBRATION
By default, the factory-set values written to the ADC offset (ADCOF) and gain coefficient registers (ADCGN) yield optimum performance in terms of end-point errors and linearity for standalone operation of the part (see the Specifications section). If system calibration is required, it is possible to modify the default offset and gain coefficients to improve end-point errors, but note that any modification to the factory-set ADCOF and ADCGN values can degrade ADC linearity performance. For system offset error correction, the ADC channel input stage must be tied to AGND. A continuous software ADC conversion loop must be implemented by modifying the value in ADCOF until the ADC result (ADCDAT) reads Code 0 to Code 1. If the ADCDAT value is greater than 1, ADCOF should be decremented until ADCDAT reads Code 0 to Code 1. Offset error correction is done digitally and has a resolution of 0.25 LSB and a range of 3.125% of VREF. For system gain error correction, the ADC channel input stage must be tied to VREF. A continuous software ADC conversion loop must be implemented to modify the value in ADCGN until the ADC result (ADCDAT) reads Code 4094 to Code 4095. If the ADCDAT value is less than 4094, ADCGN should be incremented until ADCDAT reads Code 4094 to Code 4095. Similar to the offset calibration, the gain calibration resolution is 0.25 LSB with a range of 3% of VREF. K is the gain of the ADC in temperature sensor mode as determined by characterization data. K = 0.2555C/mV. This corresponds to the 1/voltage Tc specification from Table 1. Using the default values from Table 1 and without any calibration, this equation becomes T - 25C = (VADC - 1415) x 0.2555 where VADC is in mV. For better accuracy, the user should perform a single point calibration at a controlled temperature value. For the calculation with no calibration above, use 25C and 1415 mV. The idea of a single point calibration is to use other known (TREF, VTREF) values to replace the common = 25C and 1415 mV for every part. For some users, it is not possible to get such a known pair. For such cases, the ADuC7124 comes with a single point calibration value loaded in the TEMPREF register. For more details on this register, see Table 33. During production testing of the ADuC7124, the TEMPREF register is loaded with an offset adjustment factor. Each part has a different value in the TEMPREF register. Using this single point calibration, the same formula is still used. T -- TREF = (VADC -- VTREF) x K where: TREF = 25C but is not guaranteed. VTREF can be calculated using the TEMPREF register.
TEMPERATURE SENSOR
The ADuC7124 provides voltage outputs from an on-chip band gap reference that is proportional to absolute temperature. This voltage output can also be routed through the front-end ADC multiplexer (effectively, an additional ADC channel input), facilitating an internal temperature sensor channel, measuring die temperature. An ADC temperature sensor conversion differs from a standard ADC voltage. The ADC performance specifications do not apply to the temperature sensor. Chopping of the internal amplifier must be enabled using the TSCON register. To enable this mode, the user must set Bit 0 of TSCON. The user must also take two consecutive ADC readings and average them in this mode. The ADCCON register must be configured to 0x37A3. To calculate die temperature, use the following formula: T - TREF = (VADC - VTREF) x K where: T is the temperature result. TREF = 25C. For the ADuC7124, VTREF is 1.415 V, which corresponds to TREF = 25C as described in Table 1. VADC is the average ADC result from two consecutive conversions.
TSCON Register
Name: Address: Default Value: Access: TSCON 0xFFFF0544 0x00 Read/write
Table 32. TSCON MMR Bit Designations
Bit 7 to 1 0 Description Reserved. Temperature sensor chop enable bit. This bit must be set. This bit is set to 1 to enable chopping of the internal amplifier to the ADC. This bit is cleared to disable chopping. This results in incorrect temperature sensor readings. This bit is cleared by default.
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ADuC7124
TEMPREF Register
Name: Address: Default Value: Access: TEMPREF 0xFFFF0548 0xXXXX Read/write pin (VREF) and used as a reference for other circuits in the system. An external buffer is required because of the low drive capability of the VREF output (<5 A). A programmable option also allows an external reference input on the VREF pin. Note that it is not possible to disable the internal reference. Therefore, the external reference source must be capable of overdriving the internal reference source.
Table 33. TEMPREF MMR Bit Designations
Bit 15 to 9 8 7 to 0 Description Reserved. Temperature reference voltage sign. Temperature sensor offset calibration voltage. To calculate the VTEMP from the TEMPREF register, perform the following calculation: If TEMPREF sign is negative, CTREF = 2292 - TEMPREF[7:0] where: TEMPREF[8] = 1 Or If TEMPREF sign is positive, CTREF = TEMPREF[7:0] + 2292 where: TEMPREF[8] = 0. Finally, VTREF = ((CTREF x VREF)/4096) x 1000 Insert VTREF into
REFCON Register
Name: Address: Default Value: Access: REFCON 0xFFFF048C 0x00 Read/write
The band gap reference interface consists of an 8-bit MMR REFCON, described in Table 34. Table 34. REFCON MMR Bit Designations
Bit 7:2 1 Description Reserved. Internal reference power-down bit. Set this bit to 1 to power down the internal reference source. This bit should be set when connecting an external reference source. Clear this bit to enable the internal reference. This bit is cleared by default. Internal reference output enable. Set by the user to connect the internal 2.5 V reference to the VREF pin. The reference can be used for external component but must be buffered. Cleared by the user to disconnect the reference from the VREF pin.
T - TREF = (VADC - VTREF) x K
Note that the ADC code value 2292 is a default value when using the TEMPREF register. It is not an exact value and must only be used with the TEMPREF register.
0
BAND GAP REFERENCE
Each ADuC7124 provides on-chip band gap references of 2.5 V, which can be used for the ADC and DAC. This internal reference also appears on the VREF pin. When using the internal reference, a 0.47 F capacitor must be connected from the external VREF pin to AGND to ensure stability and fast response during ADC conversions. This reference can also be connected to an external
To connect an external reference source to the ADuC7124, configure REFCON = 0x00. ADC and the DACs can be configured to use same or a different reference resource (see Table 64).
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ADuC7124 NONVOLATILE FLASH/EE MEMORY
The ADuC7124 incorporates Flash/EE memory technology on-chip to provide the user with nonvolatile, in-circuit reprogrammable memory space. Like EEPROM, flash memory can be programmed in-system at a byte level, although it must first be erased. The erase is performed in page blocks. As a result, flash memory is often and more correctly referred to as Flash/EE memory. Overall, Flash/EE memory represents a step closer to the ideal memory device that includes nonvolatility, in-circuit programmability, high density, and low cost. Incorporated in the ADuC7124, Flash/EE memory technology allows the user to update program code space in-circuit, without the need to replace one-time programmable (OTP) devices at remote operating nodes. Retention quantifies the ability of the Flash/EE memory to retain its programmed data over time. Again, the parts are qualified in accordance with the formal JEDEC Retention Lifetime Specification (A117) at a specific junction temperature (TJ = 85C). As part of this qualification procedure, the Flash/EE memory is cycled to its specified endurance limit (see the Flash/EE Memory section) before data retention is characterized. This means that the Flash/EE memory is guaranteed to retain its data for its fully specified retention lifetime every time the Flash/EE memory is reprogrammed. In addition, note that retention lifetime, based on the activation energy of 0.6 eV, derates with TJ as shown in Figure 38.
600
Flash/EE Memory
The ADuC7124 contains two 64 kB arrays of Flash/EE memory. In the first block, the lower 62 kB is available to the user, and the upper 2 kB of this Flash/EE program memory array contain permanently embedded firmware, allowing in-circuit serial download. The 2 kB of embedded firmware also contain a power-on configuration routine that downloads factory calibrated coefficients to the various calibrated peripherals (band gap references and so on). This 2 kB embedded firmware is hidden from user code. It is not possible for the user to read, write, or erase this page. In the second block, all 64 kB of Flash/EE memory are available to the user. The 126 kB of Flash/EE memory can be programmed in-circuit, using the serial download mode or the JTAG mode provided.
RETENTION (Years)
450
300
150
09123-085
0
30
40
55 70 85 100 125 JUNCTION TEMPERATURE (C)
135
150
Figure 38. Flash/EE Memory Data Retention
PROGRAMMING
The 62 kB of Flash/EE memory can be programmed in-circuit, using the serial download mode or the provided JTAG mode.
Flash/EE Memory Reliability
The Flash/EE memory arrays on the parts are fully qualified for two key Flash/EE memory characteristics: Flash/EE memory cycling endurance and Flash/EE memory data retention. Endurance quantifies the ability of the Flash/EE memory to be cycled through many program, read, and erase cycles. A single endurance cycle is composed of four independent, sequential events, defined as 1. 2. 3. 4. Initial page erase sequence. Read/verify sequence (single Flash/EE). Byte program sequence memory. Second read/verify sequence (endurance cycle).
Serial Downloading (In-Circuit Programming)
The ADuC7124 facilitates code download via the standard UART serial port. The parts enter serial download mode after a reset or power cycle if the BM pin is pulled low through an external 1 k resistor. Once in serial download mode, the user can download code to the full 126 kB of Flash/EE memory while the device is in-circuit in its target application hardware. An executable PC serial download is provided as part of the development system for serial downloading via the UART. The AN-724 application note describes the UART download protocol.
JTAG Access
The JTAG protocol uses the on-chip JTAG interface to facilitate code download and debug. To access the part via the JTAG interface, the P0.0/BM pin must be set high. When debugging, user code should not write to the P0.1, P0.2, and P0.3 pins. If user code toggles any of these pins, JTAG debug pods are not able to connect to the ADuC7124. If this happens, mass erase the part using the UART downloader.
In reliability qualification, every half word (16-bit wide) location of the three pages (top, middle, and bottom) in the Flash/EE memory is cycled 10,000 times from 0x0000 to 0xFFFF. As indicated in Table 1, the Flash/EE memory endurance qualification is carried out in accordance with JEDEC Retention Lifetime Specification A117 over the industrial temperature range of -40 to +125C. The results allow the specification of a minimum endurance figure over a supply temperature of 10,000 cycles.
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ADuC7124
FLASH/EE MEMORY SECURITY
The 126 kB of Flash/EE memory available to the user can be read and write protected. Bit 31 of the FEE0PRO/FEE0HID MMR protects the 126 kB from being read through JTAG and also in UART programming mode. The other 31 bits of this register protect writing to the Flash/EE memory; each bit protects four pages, that is, 2 kB. Write protection is activated for all access types. FEE1PRO and FEE1HID, similarly, protect the second 64 kB block. All 32 bits of this are used to protect four pages at a time.
FLASH/EE CONTROL INTERFACE
Table 35. FEE0DAT Register
Name FEE0DAT Address 0xFFFFF80C Default Value 0xXXXX Access R/W
FEE0DAT is a 16-bit data register. Table 36. FEE0ADR Register
Name FEE0ADR Address 0xFFFFF810 Default Value 0x0000 Access R/W
Three Levels of Protection
* * Protection can be set and removed by writing directly into FEExHID MMR. This protection does not remain after reset. Protection can be set by writing into FEExPRO MMR. It takes effect only after a save protection command (0x0C) and a reset. The FEExPRO MMR is protected by a key to avoid direct access. The key is saved once and must be entered again to modify FEExPRO. A mass erase sets the key back to 0xFFFF but also erases all the user code. Flash can be permanently protected by using the FEExPRO MMR and a particular value of key: 0xDEADDEAD. Entering the key again to modify the FEExPRO register is not allowed. Write the bit in FEExPRO corresponding to the page to be protected. Enable key protection by setting Bit 6 of FEExMOD (Bit 5 must equal 0). Write a 32-bit key in FEExADR and FEExDAT. Run the write key command 0x0C in FEExCON; wait for the read to be successful by monitoring FEExSTA. Reset the part.
FEE0ADR is a 16-bit address register. Table 37. FEE0SGN Register
Name FEE0SGN Address 0xFFFFF818 Default Value 0xFFFFFF Access R
FEE0SGN is a 24-bit code signature. Table 38. FEE0PRO Register
Name FEE0PRO Address 0xFFFFF81C Default Value 0x00000000 Access R/W
*
FEE0PRO provides protection following subsequent reset MMR. It requires a software key (see Table 54). Table 39. FEE0HID Register
Name FEE0HID Address 0xFFFFF820 Default Value 0xFFFFFFFF Access R/W
Sequence to Write the Key
1. 2. 3. 4. 5.
FEE0HID provides immediate protection MMR. It does not require any software keys (see Table 54). Table 40. FEE1DAT Register
Name FEE1DAT Address 0xFFFFF88C Default Value 0xXXXX Access R/W
FEE1DAT is a 16-bit data register. Table 41. FEE1ADR Register
Name FEE1ADR Address 0xFFFFF890 Default Value 0x0000 Access R/W
To remove or modify the protection, the same sequence is used with a modified value of FEExPRO. If the key chosen is the value 0xDEAD, the memory protection cannot be removed. Only a mass erase unprotects the part, but it also erases all user code. The sequence to write the key is illustrated in the following example (this protects writing Page 4 to Page 7 of the Flash):
FEExPRO=0xFFFFFFFD; Page 7 FEExMOD=0x48; FEExADR=0x1234; FEExDAT=0x5678; FEExCON= 0x0C; //Protect Page 4 to //Write key enable //16 bit key value //16 bit key value //Write key command
FEE1ADR is a 16-bit address register. Table 42. FEE1SGN Register
Name FEE1SGN Address 0xFFFFF898 Default Value 0xFFFFFF Access R
FEE1SGN is a 24-bit code signature. Table 43. FEE1PRO Register
Name FEE1PRO Address 0xFFFFF89C Default Value 0x00000000 Access R/W
The same sequence should be followed to protect the part permanently with FEExADR = 0xDEAD and FEExDAT = 0xDEAD.
FEE1PRO provides protection following subsequent reset MMR. It requires a software key (see Table 55).
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Table 44. FEE1HID Register
Name FEE1HID Address 0xFFFFF8A0 Default Value 0xFFFFFFFF Access R/W
Table 48. FEE1MOD Register
Name FEE1MOD Address 0xFFFFF884 Default Value 0x80 Access R/W
FEE1HID provides immediate protection MMR. It does not require any software keys (see Table 55). Table 45. FEE0STA Register
Name FEE0STA Address 0xFFFFF800 Default Value 0x0000 Access R/W
Table 49. FEE0CON Register
Name FEE0CON Address 0xFFFFF808 Default Value 0x00 Access R/W
Table 50. FEE1CON Register
Name FEE1CON Address 0xFFFFF888 Default Value 0x00 Access R/W
Table 46. FEE1STA Register
Name FEE1STA Address 0xFFFFF880 Default Value 0x0000 Access R/W
Command Sequence for Executing a Mass Erase
FEE0DAT = 0x3CFF; FEE0ADR = 0xFFC3; FEE0MOD = FEE0MOD|0x8; //Erase key enable FEE0CON = 0x06; //Mass erase command
Table 47. FEE0MOD Register
Name FEE0MOD Address 0xFFFFF804 Default Value 0x80 Access R/W
Table 51. FEExSTA MMR Bit Designations
Bit 15:6 5 4 3 Description Reserved. Reserved. Reserved. Flash/EE interrupt status bit. Set automatically when an interrupt occurs, that is, when a command is complete and the Flash/EE interrupt enable bit in the FEExMOD register is set. Cleared when reading the FEExSTA register. Flash/EE controller busy. Set automatically when the controller is busy. Cleared automatically when the controller is not busy. Command fail. Set automatically when a command completes unsuccessfully. Cleared automatically when reading the FEExSTA register. Command complete. Set by MicroConverter when a command is complete. Cleared automatically when reading the FEExSTA register.
2
1
0
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ADuC7124
Table 52. FEExMOD MMR Bit Designations
Bit 7:5 4 Description Reserved. Flash/EE interrupt enable. Set by the user to enable the Flash/EE interrupt. The interrupt occurs when a command is complete. Cleared by the user to disable the Flash/EE interrupt. Erase/write command protection. Set by the user to enable the erase and write commands. Cleared to protect the Flash/EE memory against the erase/write command. Reserved. Should always be set to 0 by the user. Flash/EE wait states. Both Flash/EE blocks must have the same wait state value for any change to take effect. Command Null Single read Single write Erase/write Single verify Single erase Mass erase Reserved Reserved Reserved Reserved Signature Protect Reserved Reserved Ping Description Idle state. Load FEExDAT with the 16-bit data indexed by FEExADR. Write FEExDAT at the address pointed to by FEExADR. This operation takes 50 s. Erase the page indexed by FEExADR and write FEExDAT at the location pointed to by FEExADR. This operation takes 20 ms. Compare the contents of the location pointed to by FEExADR to the data in FEExDAT. The result of the comparison is returned in FEExSTA Bit 1. Erase the page indexed by FEExADR. Erase user space. The 2 kB of kernel are protected in Block 0. This operation takes 2.48 sec. To prevent accidental execution, a command sequence is required to execute this instruction. Reserved. Reserved. Reserved. Reserved. Gives a signature of the 64 kB of Flash/EE in the 24-bit FEExSIGN MMR. This operation takes 32,778 clock cycles. This command can be run only once. The value of FEExPRO is saved and can be removed only with a mass erase (0x06) or with the key. Reserved. Reserved. No operation, interrupt generated.
3
2 1:0 Code 0x001 0x011 0x021 0x031 0x041 0x051 0x061 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
1
Table 53. Command Codes in FEExCON
The FEExCON register always reads 0x07 immediately after execution of any of these commands.
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ADuC7124
Table 54. FEE0PRO and FEE0HID MMR Bit Designations
Bit 31 Description Read protection. Cleared by the user to protect Block 0. Set by the user to allow reading of Block 0. Write protection for Page 123 to Page 120, for Page 119 to Page 116, and for Page 0 to Page 3. Cleared by the user to protect the pages in writing. Set by the user to allow writing to the pages. Description Read protection. Cleared by the user to protect Block 1. Set by the user to allow reading of Block 1. Write protection for Page 127 to Page 120. Cleared by the user to protect the pages in writing. Set by the user to allow writing to the pages. Write protection for Page 119 to Page 116 and for Page 0 to Page 3. Cleared by the user to protect the pages in writing. Set by the user to allow writing to the pages.
Flash/EE, an extra clock cycle is needed to decode the address of the data, and two cycles are needed to get the 32-bit data from Flash/EE. An extra cycle must also be added before fetching another instruction. Data transfer instructions are more complex and are summarized in Table 56. Table 56. Execution Cycles in ARM/Thumb Mode
Instructions LD1 LDH LDM/PUSH STR1 STRH STRM/POP
1
30:0
Table 55. FEE1PRO and FEE1HID MMR Bit Designations
Bit 31
Fetch Cycles 2/1 2/1 2/1 2/1 2/1 2/1
Dead Time 1 1 N2 1 1 N1
Data Access 2 1 2 x N2 2 x 20 ns 20 ns 2 x N x 20 ns1
Dead Time 1 1 N1 1 1 N1
30
The SWAP instruction combines an LD and STR instruction with only one fetch, giving a total of eight cycles + 40 ns. 2 N is the number of data bytes to load or store in the multiple load/store instruction (1 < N 16).
29:0
RESET AND REMAP
The ARM exception vectors are all situated at the bottom of the memory array, from Address 0x00000000 to Address 0x00000020, as shown in Figure 39.
0xFFFFFFFF
EXECUTION TIME FROM SRAM AND FLASH/EE
This section describes SRAM and Flash/EE access times during execution for applications where execution time is critical.
Execution from SRAM
Fetching instructions from SRAM takes one clock cycle because the access time of the SRAM is 2 ns, and a clock cycle is 24 ns minimum. However, if the instruction involves reading or writing data to memory, one extra cycle must be added if the data is in SRAM (or three cycles if the data is in Flash/EE): one cycle to execute the instruction and two cycles to get the 32-bit data from Flash/EE. A control flow instruction (a branch instruction, for example) takes one cycle to fetch but also takes two cycles to fill the pipeline with the new instructions.
KERNEL INTERRUPT SERVICE ROUTINES 0x0009F800 FLASH/EE 0x00080000
0x00047FFF INTERRUPT SERVICE ROUTINES SRAM 0x00040000
MIRROR SPACE ARM EXCEPTION VECTOR ADDRESSES 0x00000020 0x00000000 0x00000000
09123-027
Execution from Flash/EE
Because the Flash/EE width is 16 bits and access time for 16-bit words is 22 ns, execution from Flash/EE cannot be done in one cycle (as can be done from SRAM when the CD bit = 0). Also, some dead times are needed before accessing data for any value of the CD bits. In ARM mode, where instructions are 32 bits, two cycles are needed to fetch any instruction when CD = 0. In Thumb mode, where instructions are 16 bits, one cycle is needed to fetch any instruction. Timing is identical in both modes when executing instructions that involve using the Flash/EE for data memory. If the instruction to be executed is a control flow instruction, an extra cycle is needed to decode the new address of the program counter, and then four cycles are needed to fill the pipeline. A data processing instruction involving only the core register does not require any extra clock cycles. However, if it involves data in
Figure 39. Remap for Exception Execution
By default, and after any reset, the Flash/EE is mirrored at the bottom of the memory array. The remap function allows the programmer to mirror the SRAM at the bottom of the memory array, which facilitates execution of exception routines from SRAM instead of from Flash/EE. This means exceptions are executed twice as fast, being executed in 32-bit ARM mode with 32-bit wide SRAM instead of 16-bit wide Flash/EE memory.
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ADuC7124
Table 57. REMAP MMR Bit Designations (Address = 0xFFFF0220. Default Value = 0x00)
Bit 0 Name Remap Description Remap bit. Set by the user to remap the SRAM to Address 0x00000000. Cleared automatically after reset to remap the Flash/EE memory to address 0x00000000.
Table 58. RSTSTA MMR Bit Designations
Bit 7:3 2 Description Reserved. Software reset. Set by the user to force a software reset. Cleared by setting the corresponding bit in RSTCLR. Watchdog timeout. Set automatically when a watchdog timeout occurs. Cleared by setting the corresponding bit in RSTCLR. Power-on reset. Set automatically when a power-on reset occurs. Cleared by setting the corresponding bit in RSTCLR.
1
Remap Operation
When a reset occurs on the ADuC7124, execution automatically starts in factory programmed, internal configuration code. This kernel is hidden and cannot be accessed by user code. If the part is in normal mode (BM pin is high), it executes the power-on configuration routine of the kernel and then jumps to the reset vector address, 0x00000000, to execute the reset exception routine of the user. Because the Flash/EE is mirrored at the bottom of the memory array at reset, the reset interrupt routine must always be written in Flash/EE. The remap is done from Flash/EE by setting Bit 0 of the REMAP register. Caution must be taken to execute this command from Flash/EE, above Address 0x00080020, and not from the bottom of the array, because this is replaced by the SRAM. This operation is reversible. The Flash/EE can be remapped at Address 0x00000000 by clearing Bit 0 of the REMAP MMR. Caution must again be taken to execute the remap function from outside the mirrored area. Any type of reset remaps the Flash/EE memory at the bottom of the array.
0
RSTCLR Register
Name: Address: Default Value: Access: RSTCLR 0xFFFF0234 0x00 Write only
Note that to clear the RSTSTA register, users must write the Value 0x07 to the RSTCLR register.
RSTCFG Register
Name: Address: Default Value: Access: RSTCFG 0xFFFF024C 0x05 Read/write
Reset Operation
There are four kinds of reset: external, power-on, watchdog expiation, and software force. The RSTSTA register indicates the source of the last reset, and RSTCLR allows clearing of the RSTSTA register. These registers can be used during a reset exception service routine to identify the source of the reset. If RSTSTA is null, the reset is external. The RSTCFG register allows different peripherals to retain their state after a watchdog or software reset.
RSTCFG MMR Bit Designations
Bit 7:3 2 Description Reserved. Always set to 0. This bit is set to 1 to configure the DAC outputs to retain their state after a watchdog or software reset. This bit is cleared for the DAC pins and registers to return to their default state. Reserved. Always set to 0. This bit is set to 1 to configure the GPIO pins to retain their state after a watchdog or software reset. This bit is cleared for the GPIO pins and registers to return to their default state.
RSTSTA Register
Name: Address: Default Value: Access: RSTSTA 0xFFFF0230 0x01 Read only
1 0
RSTKEY0 Register
Name: Address: Default Value: Access RSTKEY0 0xFFFF0248 N/A Write only
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ADuC7124
RSTKEY1 Register
Name: Address: Default Value: Access: RSTKEY1 0xFFFF0250 N/A Write only Table 59. RSTCFG Write Sequence
Name RSTKEY1 RSTCFG RSTKEY2 Code 0x76 User value 0xB1
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ADuC7124 OTHER ANALOG PERIPHERALS
DAC
The ADuC7124 incorporates two 12-bit voltage output DACs on-chip. Each DAC has a rail-to-rail voltage output buffer capable of driving 5 k/100 pF. Each DAC has three selectable ranges: 0 V to VREF (internal band gap 2.5 V reference), 0 V to DACREF, and 0 V to AVDD. DACREF is equivalent to an external reference for the DAC. The signal range is 0 V to AVDD. Table 63. DAC0DAT MMR Bit Designations
Bit 31:28 27:16 15:0 Description Reserved. 12-bit data for DAC0. Reserved.
Using the DACs
The on-chip DAC architecture consists of a DAC resistor string followed by an output buffer amplifier. The functional equivalent is shown in Figure 40.
AVDD VREF DACREF R R DAC0
MMRs Interface
Each DAC is independently configurable through a control register and a data register. These two registers are identical for the two DACs. Only DAC0CON (see Table 61) and DAC0DAT (see Table 63) are described in detail in this section. Table 60. DACxCON Registers
Name DAC0CON DAC1CON Address 0xFFFF0600 0xFFFF0608 Default Value 0x00 0x00 Access R/W R/W
R
Table 61. DAC0CON MMR Bit Designations
Bit 7:6 5 Value Name DACCLK Description Reserved. DAC update rate. Set by the user to update the DAC using Timer1. Cleared by the user to update the DAC using HCLK (core clock). DAC clear bit. Set by the user to enable normal DAC operation. Cleared by the user to reset the data register of the DAC to 0. Reserved. This bit should be left at 0. Reserved. This bit should be left at 0. DAC range bits. Power-down mode. The DAC output is in tristate. 0 V to DACREF range. 0 V to VREF (2.5 V) range. 0 V to AVDD range.
R R
09123-023
Figure 40. DAC Structure
4
DACCLR
3 2 1:0 00 01 10 11
As illustrated in Figure 40, the reference source for each DAC is user selectable in software. It can be either AVDD, VREF, or DACREF. In 0-to-AVDD mode, the DAC output transfer function spans from 0 V to the voltage at the AVDD pin. In 0-to-DACREF mode, the DAC output transfer function spans from 0 V to the voltage at the DACREF pin. In 0-to-VREF mode, the DAC output transfer function spans from 0 V to the internal 2.5 V reference, VREF. The DAC output buffer amplifier features a true, rail-to-rail output stage implementation. This means that, when unloaded, each output is capable of swinging to within less than 5 mV of both AVDD and ground. Moreover, the DAC linearity specification (when driving a 5 k resistive load to ground) is guaranteed through the full transfer function except the 0 to 100 codes, and, in 0-to-AVDD mode only, Code 3995 to Code 4095. Linearity degradation near ground and VDD is caused by saturation of the output amplifier, and a general representation of its effects (neglecting offset and gain error) is illustrated in Figure 41. The dotted line in Figure 41 indicates the ideal transfer function, and the solid line represents what the transfer function may look like with endpoint nonlinearities due to saturation of the output amplifier. Note that Figure 41 represents a transfer function in 0-to-AVDD mode only. In 0-to-VREF or 0-to-DACREF mode (with VREF < AVDD or DACREF < AVDD), the lower nonlinearity is similar. However, the upper portion of the transfer function follows the ideal line right to the end (VREF in this case, not AVDD), showing no signs of endpoint linearity errors.
Table 62. DACxDAT Registers
Name DAC0DAT DAC1DAT Address 0xFFFF0604 0xFFFF060C Default Value 0x00000000 0x00000000 Access R/W R/W
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ADuC7124
AVDD AVDD - 100mV
Configuring DAC Buffers in Op Amp Mode
In op amp mode, the DAC output buffers are used as an op amp with the DAC itself disabled. If DACBCFG Bit 0 is set, ADC0 is the positive input to the op amp, ADC1 is the negative input, and DAC0 is the output. In this mode, the DAC should be powered down by clearing Bit 0 and Bit 1 of DAC0CON. If DACBCFG Bit 1 is set, ADC2 is the positive input to the op amp, ADC3 is the negative input, and DAC1 is the output. In this mode, the DAC should be powered down by clearing Bit 0 and Bit 1 of DAC1CON.
100mV 0x00000000 0x0FFF0000
09123-024
Figure 41. Endpoint Nonlinearities Due to Amplifier Saturation
DACBCFG Register
Name: Address: Default Value: Access: DACBCFG 0xFFFF0654 0x00 Read/write
The endpoint nonlinearities conceptually illustrated in Figure 41 get worse as a function of output loading. Most of the ADuC7124 data sheet specifications assume a 5 k resistive load to ground at the DAC output. As the output is forced to source or sink more current, the nonlinear regions at the top or bottom (respectively) of Figure 41 become larger. With larger current demands, this can significantly limit output voltage swing.
Table 65. DACBCFG MMR Bit Designations
Bit 7:2 1 Description Reserved. Always set to 0. Set this bit to 1 to configure the DAC1 output buffer in op amp mode. Clear this bit for the DAC buffer to operate as normal. Set this bit to 1 to configure the DAC0 output buffer in op amp mode. Clear this bit for the DAC buffer to operate as normal.
References to ADC and the DACs
ADC and DACs can be configured to use internal VREF or external reference as a reference source. Internal VREF must work with an external 0.47 F capacitor. Table 64. Reference Source Selection for the ADC and DAC
REFCON.0 0 0 0 0 1 1 1 DACxCON[1:0] 00 01 10 11 00 01 10 Description ADC works with an external reference. DACs are powered down. ADC works with an external reference. DAC works with DACREF. Reserved. ADC works with an external reference. DACs work with internal AVDD. ADC works with an internal VREF. DACs are power down. ADC works with an external reference. DACs work with DACREF. ADC and DACs work with an internal VREF. ADC and DACs can also work with an external reference. ADC works with an internal VREF. DACs work with an internal AVDD.
0
DACBCFG Write Sequence
DACBCFG = user value.
POWER SUPPLY MONITOR
The power supply monitor regulates the IOVDD supply on the ADuC7124. It indicates when the IOVDD supply pin drops below one of two supply trip points. The monitor function is controlled via the PSMCON register. If enabled in the IRQEN or FIQEN register, the monitor interrupts the core using the PSMI bit in the PSMCON MMR. This bit is immediately cleared once CMP goes high. This monitor function allows the user to save working registers to avoid possible data loss due to low supply or brown-out conditions. It also ensures that normal code execution does not resume until a safe supply level is established.
1
11
PSMCON Register
Name: Address: Default Value: Access: PSMCON 0xFFFF0440 0x0008 Read/write
Note that if REFCON.1 = 1, the internal VREF powers down and the ADC cannot use the internal VREF, even in Mode 1-xx.
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ADuC7124
Table 66. PSMCON MMR Bit Descriptions
Bit 3 Name CMP Description Comparator bit. This is a read-only bit that directly reflects the state of the comparator. Read 1 indicates that the IOVDD supply is above its selected trip point or, that the PSM is in power-down mode. Read 0 indicates that the IOVDD supply is below its selected trip point. This bit should be set before leaving the interrupt service routine. Trip point selection bits. 0 = 2.79 V, 1 = 3.07 V. Power supply monitor enable bit. Set to 1 to enable the power supply monitor circuit. Clear to 0 to disable the power supply monitor circuit. Power supply monitor interrupt bit. This bit is set high by the MicroConverter once CMP goes low, indicating low I/O supply. The PSMI bit can be used to interrupt the processor. Once CMP returns high, the PSMI bit can be cleared by writing a 1 to this location. A 0 write has no effect. There is no timeout delay; PSMI can be immediately cleared once CMP goes high.
Comparator Interface
The comparator interface consists of a 16-bit MMR, CMPCON, which is described in Table 67.
CMPCON Register
Name: Address: Default Value: Access: CMPCON 0xFFFF0444 0x0000 Read/write
2 1
TP PSMEN
Table 67. CMPCON MMR Bit Descriptions
Bit 15:11 10 Value Name CMPEN Description Reserved. Comparator enable bit. Set by the user to enable the comparator. Cleared by the user to disable the comparator. Comparator negative input select bits. AVDD/2. ADC3 input. DAC0 output. Reserved. Comparator output configuration bits. Reserved. Reserved. Output on CMPOUT. IRQ. Comparator output logic state bit. When low, the comparator output is high if the positive input (CMP0) is above the negative input (CMP1). When high, the comparator output is high if the positive input is below the negative input. Response time. 5 s response time typical for large signals (2.5 V differential). 17 s response time typical for small signals (0.65 mV differential). 3 s typical. Reserved. Comparator hysteresis sit. Set by user to have a hysteresis of about 7.5 mV. Cleared by user to have no hysteresis.
0
PSMI
9:8 00 01 10 11 7:6 00 01 10 11 5
CMPIN
COMPARATOR
The ADuC7124 integrates a voltage comparator. The positive input is multiplexed with ADC2, and the negative input has two options: ADC3 or DAC0. The output of the comparator can be configured to generate a system interrupt, be routed directly to the programmable logic array, start an ADC conversion, or be on an external pin, CMPOUT, as shown in Figure 42.
ADC2/CMP0 MUX ADC3/CMP1 MUX DAC0 P0.0/CMPOUT
09123-225
CMPOC
IRQ
CMPOL
Figure 42. Comparator
4:3 00
CMPRES
Hysteresis
Figure 43 shows how the input offset voltage and hysteresis terms are defined. Input offset voltage (VOS) is the difference between the center of the hysteresis range and the ground level. This can either be positive or negative. The hysteresis voltage (VH) is 1/2 the width of the hysteresis range.
CMPOUT VH VH
11 01/10 2 CMPHYST
VOS
COMP0
Figure 43. Comparator Hysteresis Transfer Function
Rev. 0 | Page 46 of 96
09123-063
ADuC7124
Bit 1 Value Name CMPORI Description Comparator output rising edge interrupt. Set automatically when a rising edge occurs on the monitored voltage (CMP0). Cleared by user by writing a 1 to this bit. Comparator output falling edge interrupt. Set automatically when a falling edge occurs on the monitored voltage (CMP0). Cleared by user.
1. 2. 3.
Enable the Timer2 interrupt and configure it for a timeout period of >120 s. Follow the write sequence to the PLLCON register, setting the MDCLK bits to 01 and clearing the OSEL bit.
0
CMPOFI
Force the part into NAP mode by following the correct write sequence to the POWCON0 register. 4. When the part is interrupted from NAP mode by the Timer2 interrupt source, the clock source has switched to the external clock. Example source code:
T2LD = 5; TCON = 0x480; while ((T2VAL == t2val_old) || (T2VAL > 3)) //ensures timer value loaded IRQEN = 0x10; //enable T2 interrupt PLLKEY1 = 0xAA; PLLCON = 0x01; PLLKEY2 = 0x55; POWKEY1 = 0x01; POWCON0 = 0x27; POWKEY2 = 0xF4;
OSCILLATOR AND PLL--POWER CONTROL
Clocking System
The ADuC7124 integrates a 32.768 kHz 3% oscillator, a clock divider, and a PLL. The PLL locks onto a multiple (1275) of the internal oscillator or an external 32.768 kHz crystal to provide a stable 41.78 MHz clock (UCLK) for the system. To allow power saving, the core can operate at this frequency or at binary submultiples of it. The actual core operating frequency, UCLK/2CD, is referred to as HCLK. The default core clock is the PLL clock divided by 8 (CD = 3) or 5.22 MHz. The core clock frequency can also come from an external clock on the ECLK pin as described in Figure 44. The core clock can be output on ECLK when using an internal oscillator or external crystal. Note that, when the ECLK pin is used to output the core clock, the output signal is not buffered and is not suitable for use as a clock source to an external device without an external buffer.
WATCHDOG TIMER INT. 32kHz* OSCILLATOR CRYSTAL OSCILLATOR OCLK XCLKO XCLKI
// Set core into nap mode
In noisy environments, noise can couple to the external crystal pins, and PLL may lose lock momentarily. A PLL interrupt is provided in the interrupt controller. The core clock is immediately halted, and this interrupt is serviced only when the lock is restored. In case of crystal loss, the watchdog timer should be used. During initialization, a test on the RSTSTA can determine if the reset came from the watchdog timer.
External Clock Selection
To switch to an external clock on P0.7, configure P0.7 in Mode 1. The external clock can be up to 41.78 MHz, providing the tolerance is 1%. Example source code:
WAKE-UP TIMER
AT POWER-UP 32.768kHz PLL 41.78MHz MDCLK I2C UCLK ANALOG PERIPHERALS P0.7/XCLK
T2LD = 5; TCON = 0x480; while ((T2VAL == t2val_old) || (T2VAL > 3)) //ensures timer value loaded
CD CORE
/2CD HCLK
09123-126
IRQEN = 0x10; //enable T2 interrupt PLLKEY1 = 0xAA; PLLCON = 0x03; //Select external clock PLLKEY2 = 0x55; POWKEY1 = POWCON0 = // Set core POWKEY2 = 0x01; 0x27; into nap mode 0xF4;
*32.768kHz 3%
P0.7/ECLK
Figure 44. Clocking System
The selection of the clock source is in the PLLCON register. By default, the part uses the internal oscillator feeding the PLL.
External Crystal Selection
To switch to an external crystal, the user must follow this procedure:
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ADuC7124
Power Control System
A choice of operating modes is available on the ADuC7124. Table 68 describes what part is powered on in the different modes and indicates the power-up time. Table 68. Operating Modes
Mode Active Pause Nap Sleep Stop Core On Peripherals On On PLL On On On XTAL/T2/T3 On On On On IRQ0 to IRQ3 On On On On On Start-Up/Power-On Time 66 ms at CD = 0 2.6 s at CD = 0; 247 s at CD = 7 2.6 s at CD = 0; 247 s at CD = 7 1.58 ms 1.7 ms
Table 69 gives some typical values of the total current consumption (analog + digital supply currents) in the different modes, depending on the clock divider bits. The AC, DAC, I2C, and SPI are turned off.
Table 69. Typical Current Consumption at 25C in mA, VDD = 3.3 V
Mode Active Pause Nap Sleep Stop CD = 0 33.3 20.6 4.6 0.2 0.2 CD = 1 23.1 12.7 4.6 0.2 0.2 CD = 2 15.4 8.8 4.6 0.2 0.2 CD = 3 11.6 6.8 4.6 0.2 0.2 CD = 4 9.7 5.8 4.6 0.2 0.2 CD = 5 8.8 5.3 4.6 0.2 0.2 CD = 6 8.3 5.1 4.6 0.2 0.2 CD = 7 8.1 4.9 4.6 0.2 0.2
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ADuC7124
MMRs and Keys
The operating mode, clocking mode, and programmable clock divider are controlled via three MMRs, PLLCON (see Table 71), and POWCONx. PLLCON controls the operating mode of the clock system, POWCON0 controls the core clock frequency and the power-down mode, and POWCON1 controls the clock frequency to I2C and SPI. To prevent accidental programming, a certain sequence must be followed to write to the PLLCON and POWCONx registers. Table 70. PLLKEYx Registers
Name PLLKEY1 PLLKEY2 Address 0xFFFF0410 0xFFFF0418 Default Value 0x0000 0x0000 Access W W
POWCON0 Register
Name: Address: Default Value: Access: POWCON0 0xFFFF0408 0x0003 Read/write
Table 74. POWCON0 MMR Bit Designations
Bit 7 6:4 Value Name PC 000 001 010 011 100 Others 3 2:0 000 001 010 011 100 101 110 111 CD Description Reserved. Operating modes. Active mode. Pause mode. Nap. Sleep mode. IRQ0 to IRQ3 and Timer2 can wake up the part. Stop mode. IRQ0 to IRQ3 can wake up the part. Reserved. Reserved. CPU clock divider bits. 41.78 MHz. 20.89 MHz. 10.44 MHz. 5.22 MHz. 2.61 MHz. 1.31 MHz. 653 kHz. 326 kHz.
PLLCON Register
Name: Address: Default Value: Access: PLLCON 0xFFFF0414 0x21 Read/write
Table 71. PLLCON MMR Bit Designations
Bit 7:6 5 Value Name OSEL Description Reserved. 32 kHz PLL input selection. Set by the user to select the internal 32 kHz oscillator. Set by default. Cleared by the user to select the external 32 kHz crystal. Reserved. Clocking modes. Reserved. PLL. Default configuration. Reserved. External clock on the P0.7 Pin.
4:2 1:0 00 01 10 11
MDCLK
Table 75. POWCON0 Write Sequence
POWCON0 POWKEY1 = 0x01 POWCON0 = user value POWKEY2 = 0xF4
Table 72. PLLCON Write Sequence
PLLCON PLLKEY1 = 0xAA PLLCON = user value PLLKEY2 = 0x55
Table 76. POWKEYx Registers
Name POWKEY3 POWKEY4 Address 0xFFFF0434 0xFFFF043C Default Value 0x0000 0x0000 Access W W
Table 73. POWKEYx Registers
Name POWKEY1 POWKEY2 Address 0xFFFF0404 0xFFFF040C Default Value 0x0000 0x0000 Access W W
POWKEY3 and POWKEY4 are used to prevent accidental programming to POWCON1.
POWCON1 Register
Name: Address: Default Value: Access: POWCON1 0xFFFF0438 0x124 Read/write
POWKEY1 and POWKEY2 are used to prevent accidental programming to POWCON0.
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ADuC7124
Table 77. POWCON1 MMR Bit Designations
Bit 15:12 11 10:9 8 7:6 00 01 10 11 5 4:3 00 01 10 11 2 1:0 00 01 10 11 I2C0PO I2C0CLKDIV I2C1PO I2C1CLKDIV Value 1 00 Name PWMPO PWMCLKDIV SPIPO SPICLKDIV Description Reserved.
Table 78. POWCON1 Write Sequence
POWCON1 POWKEY3 = 0x76 POWCON1 = user value POWKEY4 = 0XB1
Clearing this bit powers down the SPI. SPI block driving clock divider bits. 41.78 MHz. 20.89 MHz. 10.44 MHz. 5.22 MHz. Clearing this bit powers down the I2C1. I2C0 block driving clock divider bits. 41.78 MHz. 10.44 MHz. 5.22 MHz. 1.31 MHz. Clearing this bit powers down the I2C0. I2C1 block driving clock divider bits. 41.78 MHz. 10.44 MHz. 5.22 MHz. 1.31 MHz.
Rev. 0 | Page 50 of 96
ADuC7124 DIGITAL PERIPHERAL
GENERAL-PURPOSE INPUT/OUTPUT
The ADuC7124 provides 30 general-purpose, bidirectional I/O (GPIO) pins. All I/O pins are 5 V tolerant, meaning the GPIOs support an input voltage of 5 V. In general, many of the GPIO pins have multiple functions (see the Pin Configuration and Function Descriptions section for pin function definitions). By default, the GPIO pins are configured in GPIO mode. All GPIO pins have an internal pull-up resistor (of about 100 k), and their drive capability is 1.6 mA. Note that a maximum of 20 GPIOs can drive 1.6 mA at the same time. Using the GPxPAR registers, it is possible to enable/disable the pull-up resistors for the following ports: P0.0, P0.4, P0.5, P0.6, P0.7, and the eight GPIOs of P1. The 40 GPIOs are grouped in five ports, Port 0 to Port 4 (Port x). Each port is controlled by four or five MMRs. Note that the kernel changes P0.6 from its default configuration at reset (MRST) to GPIO mode. If MRST is used for external circuitry, an external pull-up resistor should be used to ensure that the level on P0.6 does not drop when the kernel switches mode. Otherwise, P0.6 goes low for the reset period. For example, if MRST is required for power-down, it can be reconfigured in GP0CON MMR. The input level of any GPIO can be read at any time in the GPxDAT MMR, even when the pin is configured in a mode other than GPIO. The PLA input is always active. When the ADuC7124 enters a power-saving mode, the GPIO pins retain their state. Also note that, by setting RSTCFG Bit 0, the GPIO pins can retain their state during a watchdog or software reset.
4 2
Table 79. GPIO Pin Function Descriptions
Port 0 Pin P0.0/BM TDI/P0.11 TDO/P0.21 nTRST/P0.31 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P4.0 P4.1 P4.2 P4.3 P4.4 P4.52 P4.6 P4.7 00 GPIO GPIO/JTAG GPIO/JTAG GPIO/JTAG GPIO/IRQ0 GPIO/IRQ1 GPIO GPIO GPIO/T1 GPIO GPIO GPIO GPIO/IRQ2 GPIO/IRQ3 GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO/RTCK GPIO GPIO Configuration 01 10 CMP MS0 PWM4 BLE PWM5 BHE TRST A16 PWMTRIP MS1 ADCBUSY MS2 MRST MS3 ECLK/XCLK2 SIN0 SIN0 SCL0 SOUT0 SDA0 RTS SCL1 CTS SDA1 RI CLK DCD MISO DSR MOSI DTR CSL SOUT0 CONVSTART3 PWM0 PWM1 PWM0 PWM1 PWM2 PWM3 PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWMTRIP PWMSYNC SIN1 SOUT1 WS RS AE MS0 MS1 MS2 MS3 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 11 PLAI[7]
1
ADCBUSY PLAO[1] PLAO[2] PLAO[3] PLAO[4] PLAI[0] PLAI[1] PLAI[2] PLAI[3] PLAI[4] PLAI[5] PLAI[6] PLAO[0] PLAO[5] PLAO[6] PLAO[7] SIN1 SOUT1
3
PLAI[8] PLAI[9] PLAI[10] PLAI[11] PLAI[12] PLAI[13] PLAI[14] PLAI[15] PLAO[8] PLAO[9] PLAO[10] PLAO[11] PLAO[12] PLAO[13] PLAO[14] PLAO[15]
1 2
These pins should not be used by user code . When configured in Mode 1, P0.7 is ECLK by default, or core clock output. To configure it as a clock input, the MDCLK bits in PLLCON must be set to 11. 3 The CONVSTART signal is active in all modes of P2.0.
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ADuC7124
Table 80. GPxCON Registers
Name GP0CON GP1CON GP2CON GP3CON GP4CON Address 0xFFFFF400 0xFFFFF404 0xFFFFF408 0xFFFFF40C 0xFFFFF410 Default Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Access R/W R/W R/W R/W R/W Bit 15 14:13 12 11 10:9 8 7 6:5 4 3 2:1 0 Description Reserved. Drive strength Px.3 Pull-up disable Px.3. Reserved. Drive strength Px.2 Pull-up disable Px.2. Reserved. Drive strength Px.1 Pull-up disable Px.1. Reserved. Drive strength Px.0 Pull-up disable Px.0.
GPxCON are the Port x control registers, which select the function of each pin of Port x as described in Table 81. Table 81. GPxCON MMR Bit Descriptions
Bit 31:30 29:28 27:26 25:24 23:22 21:20 19:18 17:16 15:14 13:12 11:10 9:8 7:6 5:4 3:2 1:0 Description Reserved. Select function of Px.7 pin. Reserved. Select function of Px.6 pin. Reserved. Select function of Px.5 pin. Reserved. Select function of Px.4 pin. Reserved. Select function of Px.3 pin. Reserved. Select function of Px.2 pin. Reserved. Select function of Px.1 pin. Reserved. Select function of Px.0 pin.
Table 84. GPIO Drive Strength Control Bits Descriptions
Control Bits Value 00 01 1x Description Medium drive strength. Low drive strength. High drive strength.
3.6 3.4 3.2 HIGH DRIVE STRENGTH MEDIUM DRIVE STRENGTH LOW DRIVE STRENGTH
SUPPLY VOLTAGE (V)
3.0 2.8 2.6 2.4
Table 82. GPxPAR Registers
Name GP0PAR GP1PAR GP2PAR GP3PAR GP4PAR Address 0xFFFFF42C 0xFFFFF43C 0xFFFFF44C 0xFFFFF45C 0xFFFFF46C Default Value 0x20000000 0x00000000 0x00000000 0x00000000 0x00000000 Access R/W R/W R/W R/W R/W
2.0 -24
-18
-12 -6 0 6 12 SINK/SOURCE CURRENT (mA)
18
24
Figure 45. Programmable Strength for High Level
0.5 0.4 0.3 HIGH DRIVE STRENGTH MEDIUM DRIVE STRENGTH LOW DRIVE STRENGTH
The GPxPAR registers program the parameters for Port 0/ Port 1/Port 2/Port 3/Port 4. Note that the GPxDAT MMR must always be written after changing the GPxPAR MMR.
SUPPLY VOLTAGE (V)
Table 83. GPxPAR MMR Bit Descriptions
Bit 31 30:29 28 27 26:25 24 23 22:21 20 19 18:17 16 Description Reserved. Drive strength Px.7 Pull-up disable Px.7. Reserved. Drive strength Px.6 Pull-up disable Px.6. Reserved. Drive strength Px.5 Pull-up disable Px.5. Reserved. Drive strength Px.4 Pull-up disable Px.4.
0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -24
09123-149
-18
-12 -6 0 6 12 SINK/SOURCE CURRENT (mA)
18
24
Figure 46. Programmable Strength for Low Level
Rev. 0 | Page 52 of 96
09123-148
2.2
ADuC7124
The drive strength bits can be written only once after reset. More writing to related bits has no effect on changing drive strength. The GPIO drive strength and pull-up disable are not always adjustable for GPIO port. Some control bits cannot be changed. See details from Table 82. Table 85. GPxDAT Registers
Name GP0DAT GP1DAT GP2DAT GP3DAT GP4DAT Address 0xFFFFF420 0xFFFFF430 0xFFFFF440 0xFFFFF450 0xFFFFF460 Default Value 0x000000XX 0x000000XX 0x000000XX 0x000000XX 0x000000XX Access R/W R/W R/W R/W R/W 15:0
Table 90. GPxCLR MMR Bit Descriptions
Bit 31:24 23:16 Description Reserved. Data Port x clear bit. Set to 1 by the user to clear a bit on Port x; also clears the corresponding bit in the GPxDAT MMR. Cleared to 0 by the user; does not affect the data out. Reserved.
SERIAL PORT MUX
The serial port mux multiplexes the serial port peripherals (an SPI, UART, and two I2Cs) and the programmable logic array (PLA) to a set of 10 GPIO pins. Each pin must be configured to one of its specific I/O functions as described in Table 91. Table 91. SPM Configuration
SPMMUX SPM0 SPM1 SPM2 SPM3 SPM4 SPM5 SPM6 SPM7 SPM8 SPM9 GPIO (00) P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P0.7 P2.0 UART (01) SIN0 SOUT0 RTS CTS RI DCD DSR DTR ECLK/XCLK CONV UART/I2C/SPI (10) I2C0SCL I2C0SDA I2C1SCL I2C1SDA SPICLK SPIMISO SPIMOSI SPICS SIN0 SOUT0 PLA (11) PLAI[0] PLAI[1] PLAI[2] PLAI[3] PLAI[4] PLAI[5] PLAI[6] PLAO[0] PLAO[4] PLAO[5]
The GPxDAT are Port x configuration and data registers. They configure the direction of the GPIO pins of Port x, set the output value for the pins configured as output, and store the input value of the pins configured as input. Table 86. GPxDAT MMR Bit Descriptions
Bit 31:24 Description Direction of the data. Set to 1 by the user to configure the GPIO pin as an output. Cleared to 0 by the user to configure the GPIO pin as an input. Port x data output. Reflect the state of Port x pins at reset (read only). Port x data input (read only).
23:16 15:8 7:0
Table 87. GPxSET Registers
Name GP0SET GP1SET GP2SET GP3SET GP4SET Address 0xFFFFF424 0xFFFFF434 0xFFFFF444 0xFFFFF454 0xFFFFF464 Default Value 0x000000XX 0x000000XX 0x000000XX 0x000000XX 0x000000XX Access W W W W W
Table 91 also details the mode for each of the SPMMUX pins. This configuration has to be done via the GP0CON, GP1CON, and GP2CON MMRs. By default, these 10 pins are configured as GPIOs.
UART SERIAL INTERFACE
The UART peripheral is a full-duplex, universal, asynchronous receiver/transmitter. The UART performs serial-to-parallel conversions on data characters received from a peripheral device and parallel-to-serial conversions on data characters received from the CPU. The ADuC7124 has been equipped with two industry standard 16,450 type UARTs(UART0 and UART1). Each UART features a fractional divider that facilitates high accuracy baud rate generation and is equipped with a 16-byte FIFO for the transmitter and a 16-byte FIFO for the receiver. Both UARTs can be configured as FIFO mode and non-FIFO mode. The serial communication adopts an asynchronous protocol, which supports various word lengths, stop bits, and parity generation options selectable in the configuration register.
The GPxSET are data set Port x registers. Table 88. GPxSET MMR Bit Descriptions
Bit 31:24 23:16 Description Reserved. Data Port x set bit. Set to 1 by the user to set a bit on Port x; also sets the corresponding bit in the GPxDAT MMR. Cleared to 0 by the user; does not affect the data out. Reserved.
15:0
Table 89. GPxCLR Registers
Name GP0CLR GP1CLR GP2CLR GP3CLR GP4CLR Address 0xFFFFF428 0xFFFFF438 0xFFFFF448 0xFFFFF458 0xFFFFF468 Default Value 0x000000XX 0x000000XX 0x000000XX 0x000000XX 0x000000XX Access W W W W W
Baud Rate Generation
There are two ways of generating the UART baud rate, using normal 450 UART baud rate generation and using the fractional divider.
The GPxCLR are data clear Port x registers.
Rev. 0 | Page 53 of 96
ADuC7124
Normal 450 UART Baud Rate Generation
The baud rate is a divided version of the core clock using the value in the COMDIV0 and COMDIV1 MMRs (16-bit value, DL).
UART Register Definitions COM0TX Register
Name: Address: Default Value: Access: COM0TX 0xFFFF0700 0x00 Read/write
Baud Rate =
41.78 MHz 2 CD x 16 x 2 x DL
Table 92 gives some common baud rate values. Table 92. Baud Rate Using the Normal Baud Rate Generator
Baud Rate 9600 19,200 115,200 9600 19,200 115,200 CD 0 0 0 3 3 3 DL 0x88 0x44 0x0B 0x11 0x08 0x01 Actual Baud Rate 9600 19,200 118,691 9600 20,400 163,200 % Error 0 0 3 0 6.25 41.67
COM0TX is an 8-bit transmit register for UART0.
COM1TX Register
Name: Address: Default Value: Access: COM1TX 0xFFFF0740 0x00 Read/write
The Fractional Divider
The fractional divider, combined with the normal baud rate generator, produces a wider range of more accurate baud rates.
CORE CLOCK /2 FBEN
COM1TX is an 8-bit transmit register for UART1.
COM0RX Register
Name:
09123-032
COM0RX 0xFFFF0700 0x00 Read only
/ 16DL / (M + N / 2048)
UART
Address: Default Value: Access:
Figure 47. Baud Rate Generation Options
Calculation of the baud rate using fractional divider is as follows:
Baud Rate =
41.78 MHz N 2 CD x 16 x DL x 2 x M + 2048
COM0RX is an 8-bit receive register for UART0.
COM1RX Register
Name: Address: Default Value: Access: COM1RX 0xFFFF0740 0x00 Read only
M+
41.78 MHz N = 2048 Baud Rate x 2 CD x 16 x DL x 2
For example, generation of 19,200 baud with CD bits = 3 (Table 92 gives DL = 0x08) is
M+
M+
41.78 MHz N = 2048 19,200 x 2 3 x 16 x 8 x 2
N = 1.06 2048
COM1RX is an 8-bit receive register for UART1.
COM0DIV0 Register
Name: Address: Default Value:
41.78 MHz
COM0DIV0 0xFFFF0700 0x00 Read/write
where: M = 1. N = 0.06 x 2048 = 128.
Baud Rate = 128 2 3 x 16 x 8 x 2 x 2048
Access:
where: Baud Rate = 19,200 bps. Error = 0%, compared to 6.25% with the normal baud rate generator.
COM0DIV0 is a low byte divisor latch for UART0. COM0TX, COM0RX, and COM0DIV0 share the same address location. COM0TX and COM0RX can be accessed when Bit 7 in the COM0CON0 register is cleared. COM0DIV0 can be accessed when Bit 7 of COM0CON0 is set.
Rev. 0 | Page 54 of 96
ADuC7124
COM1DIV0 Register
Name: Address: Default Value: Access: COM1DIV0 0xFFFF0740 0x00 Read/write
COM0DIV1 Register
Name: Address: Default Value: Access: COM0DIV1 0xFFFF0704 0x00 Read/write
COM1DIV0 is a low byte divisor latch for UART1. COM1TX, COM1RX, and COM1DIV0 share the same address location. COM1TX and COM1RX can be accessed when Bit 7 in COM1CON0 register is cleared. COM1DIV0 can be accessed when Bit 7 of COM1CON0 is set.
COM0DIV1 is a divisor latch (high byte) register for UART0.
COM1DIV1 Register
Name: Address: Default Value: Access: COM1DIV1 0xFFFF0744 0x00 Read/write
COM0IEN0 Register
Name: Address: Default Value: Access: COM0IEN0 0xFFFF0704 0x00 Read/write
COM1DIV1 is a divisor latch (high byte) register for UART1.
COM0IID0 Register
Name: Address: Default Value: Access: COM0IID0 0xFFFF0708 0x01 Read only
COM0IEN0 is the interrupt enable register for UART0.
COM1IEN0 Register
Name: Address: Default Value: Access: COM1IEN0 0xFFFF0744 0x00 Read/write
COM0IID0 is the interrupt identification register for UART0. It also indicatesif the UART is at FIFO mode.
COM1IID0 Register
Name: Address: Default Value: Access: COM1IID0 0xFFFF0748 0x01 Read only
COM1IEN0 is the interrupt enable register for UART1. Table 93. COMxIEN0 MMR Bit Descriptions
Bit 7:4 3 Name EDSSI Description Reserved. Modem status interrupt enable bit. Set by the user to enable generation of an interrupt if any of COMXSTA1[3:1] are set. Cleared by the user. Rx status interrupt enable bit. Set by the user to enable generation of an interrupt if any of COMxSTA0[3:0] are set. Cleared by the user. Enable transmit buffer empty interrupt. Set by the user to enable interrupt when buffer is empty during a transmission. Cleared by the user. Enable receive buffer full interrupt. In non-FIFO mode, set by the user to enable interrupt when buffer is full during a reception. Cleared by the user. In FIFO mode, set by the user to enable interrupt when trigger level is reached. It also controls the character receive time-out interrupt. Cleared by the user.
COM1IID0 is the interrupt identification register for UART1. It also indicates if the UART is at FIFO mode.
2
ELSI
1
ETBEI
0
ERBFI
Rev. 0 | Page 55 of 96
ADuC7124
Table 94. COMxIID0 MMR Bit Descriptions
Bit 7:6 Name FIFOMODE Description FIFO mode flag. 0x0: non-FIFO mode. 0x1: reserved. 0x2: reserved. 0x3: FIFO mode. Set automatically if FIFOEN is set. Interrupt status bits that work only when NINT is set. [000]: modem status interrupt. Cleared by reading COMxSTA1. Priority 4. [001]: for non-FIFO mode, transmit buffer empty interrupt. For FIFO mode, TXFIFO is empty. Cleared by writing COMxTX or reading COMxIID0. Priority 3. [010]: non-FIFO mode. Receive buffer data ready interrupt. Cleared automatically by reading COMxRX. For FIFO mode, set trigger level reached. Cleared automatically when FIFO drops below the trigger level. Priority 2. [011]: receive line status error interrupt. Cleared by reading COMxSTA0. Priority 1. [110]: RXFIFO timeout interrupt (FIFO mode only). Set automatically if there is at least one byte in RXFIFO, and there is no access to RXFIFO in the next four-frames accessing cycle. Cleared by read COMxRX, set RXRST or when a new byte arrives in RXFIFO1. Priority 2. [Other state]: reserved. Set to disable interrupt flags by STATUS. Clear to enable interrupt.
COM1FCR Register
Name: Address: Default Value: Access: COM1FCR 0xFFFF0748 0x00 Write only
5:4 3:1
Reserved STATUS[2:0]
The FIFO control register (FCR) is a write-only register at the same address as the interrupt identification register (IIR), which is a read-only register. Table 95. COMxFCR MMR Bit Descriptions
Bit 7:5 Name RXFIFOTL Description Receiver FIFO trigger level. RXFIFTL sets the trigger level for the receiver FIFO. When the trigger level is reached, a receiver data-ready interrupt is generated (if the interrupt request is enabled). Once the FIFO drops below the trigger level, the interrupt is cleared. 0x0: one byte. 0x1: two bytes. 0x2: four bytes. 0x3: six bytes. 0x4: eight bytes. 0x5: 10 bytes. 0x6: 12 bytes. 0x7: 14 bytes. TXFIFO reset. Writing a 1 flushes the TXFIFO. Does not affect shift register. Note that TXRST should be cleared manually to make TXFIFO work after flushing. RXFIFO reset. Writing a 1 flushes the RXFIFO. Does not affect shift register. Note that RXRST should be cleared manually to make RXFIFO work after flushing. Transmitter and receiver FIFOs mode enable. FIFOEN must be set before other FCR bits are written to. Set for FIFO mode. The transmitter and receiver FIFOs are enabled. Cleared for non-FIFO mode; the transmitter and receiver FIFOs are disabled, and the FIFO pointers are cleared.
4:3 2
Reserved TXRST
0
1
NINT
1
RXRST
A frame time is the time allotted for one start bit, n data bits, one parity bit, and one stop bit. Here, n is the word length selected with the WLS bits in COMxCON0. WLS[1:0] = 00: timeout threshold = time for 32 bits = (1 + 5 + 1 + 1) x 4. WLS[1:0] = 01: timeout threshold = time for 36 bits = (1 + 6 + 1 + 1) x 4. WLS[1:0] = 10: timeout threshold = time for 40 bits = (1 + 7 + 1 + 1) x 4. WLS[1:0] = 11: timeout threshold = time for 44 bits = (1 + 8 + 1 + 1) x 4.
0
FIFOEN
COM0FCR Register
Name: Address: Default Value: Access: COM0FCR 0xFFFF0708 0x00 Write only
COM0CON0 Register
Name: Address: Default Value: Access: COM0CON0 0xFFFF070C 0x00 Read/write
The FIFO control register (FCR) is a write-only register at the same address as the interrupt identification register (IIR), which is a read-only register.
COM0CON0 is the line control register for UART0.
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ADuC7124
COM1CON0 Register
Name: Address: Default Value: Access: COM1CON0 0xFFFF074C 0x00 Read/write
COM1CON1 Register
Name: Address: Default Value: Access: COM1CON1 0xFFFF0750 0x00 Read/write
COM1CON0 is the line control register for UART1. Table 96. COMxCON0 MMR Bit Descriptions
Bit 7 Name DLAB Description Divisor latch access. Set by the user to enable access to the COMxDIV0 and COMxDIV1 registers. Cleared by the user to disable access to COMxDIV0 and COMxDIV1 and enable access to COMxRX and COMxTX. Set break. Set by the user to force SOUT to 0. Cleared to operate in normal mode. Stick parity. Set by the user to force parity to defined values: 1 if EPS = 1 and PEN = 1, 0 if EPS = 0 and PEN = 1. Even parity select bit. Set for even parity. Cleared for odd parity. Parity enable bit. Set by the user to transmit and check the parity bit. Cleared by the user for no parity transmission or checking. Stop bit. Set by the user to transmit 1.5 stop bits if the word length is five bits or two stop bits if the word length is six bits, seven bits, or eight bits. The receiver checks the first stop bit only, regardless of the number of stop bits selected. Cleared by the user to generate one stop bit in the transmitted data. Word length select: 00 = five bits, 01 = six bits, 10 = seven bits, 11 = eight bits.
COM1CON1 is the modem control register for UART1. Table 97. COMxCON1 MMR Bit Descriptions
Bit 7:5 4 Name LOOPBACK Description Reserved. Loop back. Set by the user to enable loopback mode. In loop-back mode, SOUT is forced high. The modem signals are also directly connected to the status inputs (RTS to CTS and DTR to DSR). Cleared by the user to be in normal mode. Parity enable bit. Set by the user to transmit and check the parity bit. Cleared by the user for no parity transmission or checking. Stop bit. Set by the user to transmit 1.5 stop bits if the word length is five bits or two stop bits if the word length is six bits, seven bits, or eight bits. The receiver checks the first stop bit only, regardless of the number of stop bits selected. Cleared by the user to generate one stop bit in the transmitted data. Request to send. Set by the user to force the RTS output to 0. Cleared by the user to force the RTS output to 1. Data terminal ready. Set by the user to force the DTR output to 0. Cleared by the user to force the DTR output to 1.
6
BRK
3
PEN
5
SP
4
EPS
2
STOP
3
PEN
2
STOP
1
RTS
0
DTR
1:0
WLS
COM0CON1 Register
Name: Address: Default Value: Access: COM0CON1 0xFFFF0710 0x00 Read/write
COM0STA0 Register
Name: Address: Default Value: Access: COM0STA0 0xFFFF0714 0xE0 Read only
COM0CON1 is the modem control register for UART0.
COM0STA0 is the line status register for UART0.
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ADuC7124
COM1STA0 Register
Name: Address: Default Value: Access: COM1STA0 0xFFFF0754 0xE0 Read only
Bit 1 Name OE Description Overrun error. For non-FIFO mode, set automatically if data is overwritten before being read. Cleared automatically. For FIFO mode, set automatically if an overrun error has been detected. An overrun error occurs only after the FIFO is full and the next character has been completely received in the shift register. The new character overwrites the character in the shift register, but it is not transferred to the FIFO. Data ready. For non-FIFO mode, set automatically when COMxRX is full. Cleared by reading COMxRX. For FIFO mode, set automatically when there is at least one unread byte in the COMxRX.
COM1STA0 is the line status register for UART1. Table 98. COMxSTA0 MMR Bit Descriptions
Bit 11 Name RX_error Description Set automatically if PE, FE, or BI is set. Cleared automatically when PE, FE and BI are cleared . Only for FIFO mode. Set automatically if there is at least one byte in RXFIFO and there is no access to RXFIFO in the next four-bytes accessing cycle. Only for FIFO mode. Set automatically if the RXFIFO number exceeds the trigger level, which is configured by the FIFO control register COMxFCR[7:5]. Cleared automatically when RXFIFO number is equal to or less than the trigger level. Only for FIFO mode. Set automatically if TXFIFO full. Cleared automatically when TXFIFO is not full. Only for FIFO mode. Set automatically if TXFIFO is half empty (number of bytes in TXFIFO 8). Cleared automatically when TXFIFO received bytes is more than eight bytes. COMxTX empty status bit. For non-FIFO mode, both THR and TSR are empty. For FIFO mode, both TXFIFO and TSR are empty. COMxTX and transmitter shift register empty. For non-FIFO mode, transmitter hold register (THR) empty or the content of THR has been transferred to the transmitter shift register (TSR). For FIFO mode, TXFIFO empty, or the last character in the FIFO has been transferred to the transmitter shift register (TSR). Break error. Set when SIN is held low for more than the maximum word length. Cleared automatically. Framing error. Set when an invalid stop bit occurs. Cleared automatically. Parity error. Set when a parity error occurs. Cleared automatically. 0 DR
10
RX_timeout
9
RX_triggered
COM0STA1 Register
Name: Address: Default Value: Access: COM0STA1 0xFFFF0718 0x00 Read only
8
TX_full
7
TX_half_empty
COM0STA1 is a modem status register.
COM1STA1 Register
Name: Address: Default Value: Access: COM1STA1 0xFFFF0758 0x00 Read only
6
TEMT
5
THRE
COM1STA1 is a modem status register. Table 99. COMxSTA1 MMR Bit Descriptions
Bit 7 6 5 4 3 Name DCD RI DSR CTS DDCD Description Data carrier detect. Ring indicator. Data set ready. Clear to send. Delta DCD. Set automatically if DCD changed state since last COMxSTA1 read. Cleared automatically by reading COMxSTA1. Trailing edge RI. Set if RI changed from 0 to 1 since COMxSTA1 last read. Cleared automatically by reading COMxSTA1. Delta DSR. Set automatically if DSR changed state since COMxSTA1 last read. Cleared automatically by reading COMxSTA1. Delta CTS. Set automatically if CTS changed state since COMxSTA1 last read. Cleared automatically by reading COMxSTA1.
4
BI
2
TERI
3
FE
1
DDSR
2
PE
0
DCTS
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ADuC7124
COM0DIV2 Register
Name: Address: Default Value: Access: COM0DIV2 0xFFFF072C 0x0000 Read/write the slave device (data in). The data is transferred as byte wide (8-bit) serial data, MSB first.
SPICLK(Serial Clock I/O) Pin
The master serial clock (SPICLK) synchronizes the data being transmitted and received through the MOSI SPICLK period. Therefore, a byte is transmitted/received after eight SPICLK periods. The SPICLK pin is configured as an output in master mode and as an input in slave mode. In master mode, polarity and phase of the clock are controlled by the SPICON register, and the bit rate is defined in the SPIDIV register as follows:
COM0DIV2 is a 16-bit fractional baud divide register for UART0.
COM1DIV2 Register
Name: Address: Default Value: Access: COM1DIV2 0xFFFF076C 0x0000 Read/write
f SERIAL CLOCK =
f UCLK 2 x (1 + SPIDIV )
The maximum speed of the SPI clock is independent of the clock divider bits. In slave mode, the SPICON register must be configured with the phase and polarity of the expected input clock. The slave accepts data from an external master up to 10 Mbps. In both master and slave modes, data is transmitted on one edge of the SPICLK signal and sampled on the other. Therefore, it is important that the polarity and phase be configured the same for the master and slave devices.
COM1DIV2 is a 16-bit fractional baud divide register for UART1. Table 100. COMxDIV2 MMR Bit Descriptions
Bit 15 Name FBEN Description Fractional baud rate generator enable bit. Set by the user to enable the fractional baud rate generator. Cleared by the user to generate the baud rate using the standard 450 UART baud rate generator. Reserved. M if FBM = 0, M = 4 (see The Fractional Divider section). N (see The Fractional Divider section).
SPI Chip Select (SPICS Input) Pin
In SPI slave mode, a transfer is initiated by the assertion of SPICS, which is an active low input signal. The SPI port then transmits and receives 8-bit data until the transfer is concluded by deassertion of SPICS. In slave mode, SPICS is always an input. In SPI master mode, the SPICS is an active low output signal. It asserts itself automatically at the beginning of a transfer and deasserts itself upon completion.
14:13 12:11 10:0
FBM[1:0] FBN[10:0]
SERIAL PERIPHERAL INTERFACE
The ADuC7124 integrates a complete hardware serial peripheral interface (SPI) on-chip. SPI is an industry standard, synchronous serial interface that allows eight bits of data to be synchronously transmitted and simultaneously received, that is, full duplex up to a maximum bit rate of 20 Mbps. The SPI port can be configured for master or slave operation and typically consists of four pins: SPIMISO, SPIMOSI, SPICLK, and SPICS.
Configuring External Pins for SPI functionality
The SPI pins of the ADuC7124 device are P1.4 to P1.7. P1.7 is the slave chip select pin. In slave mode, this pin is an input and must be driven low by the master. In master mode, this pin is an output and goes low at the beginning of a transfer and high at the end of a transfer. P1.4 is the SPICLK pin. P1.5 is the master in, slave out (SPIMISO) pin. P1.6 is the master out, slave in (SPIMOSI) pin. To configure P1[4:7] for SPI mode, see the General-Purpose Input/Output section.
SPIMISO (Master In, Slave Out) Pin
The SPIMISO pin is configured as an input line in master mode and an output line in slave mode. The SPIMISO line on the master (data in) should be connected to the SPIMISO line in the slave device (data out). The data is transferred as byte wide (8-bit) serial data, MSB first.
SPI Registers
The following MMR registers control the SPI interface: SPISTA, SPIRX, SPITX, SPIDIV, and SPICON.
SPIMOSI (Master Out, Slave In) Pin
The SPIMOSI pin is configured as an output line in master mode and an input line in slave mode. The SPIMOSI line on the master (data out) should be connected to the SPIMOSI line in
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ADuC7124
SPI Status Register
Name: Address: Default Value: Access: Function: SPISTA 0xFFFF0A00 0x0000 Read/write This 32-bit MMR contains the status of the SPI interface in both master and slave modes.
Table 101. SPISTA MMR Bit Designations
Bit 15:12 11 Name SPIREX Description Reserved bits. SPI Rx FIFO excess bytes present. This bit is set when there are more bytes in the Rx FIFO than indicated in the SPIMDE bits in SPICON This bit is cleared when the number of bytes in the FIFO is equal to or less than the number in SPIMDE. SPI Rx FIFO status bits. [000] = Rx FIFO is empty. [001] = one valid byte in the FIFO. [010] = two valid bytes in the FIFO. [011] = three valid bytes in the FIFO. [100] = four valid bytes in the FIFO. SPI Rx FIFO overflow status bit. Set when the Rx FIFO was already full when new data was loaded to the FIFO. This bit generates an interrupt except when SPIRFLH is set in SPICON. Cleared when the SPISTA register is read. SPI Rx IRQ status bit. Set when a receive interrupt occurs. This bit is set when SPITMDE in SPICON is cleared and the required number of bytes has been received. Cleared when the SPISTA register is read. SPI Tx IRQ status bit. Set when a transmit interrupt occurs. This bit is set when SPITMDE in SPICON is set and the required number of bytes has been transmitted. Cleared when the SPISTA register is read. SPI Tx FIFO underflow. This bit is set when a transmit is initiated without any valid data in the Tx FIFO. This bit generates an interrupt except when SPITFLH is set in SPICON. Cleared when the SPISTA register is read. SPI Tx FIFO status bits. [000] = Tx FIFO is empty. [001] = one valid byte in the FIFO. [010] = two valid bytes in the FIFO. [011] = three valid bytes in the FIFO. [100] = four valid bytes in the FIFO. SPI interrupt status bit. Set to 1 when an SPI-based interrupt occurs. Cleared after reading SPISTA.
10:8
SPIRXFSTA[2:0]
7
SPIFOF
6
SPIRXIRQ
5
SPITXIRQ
4
SPITXUF
3:1
SPITXFSTA[2:0]
0
SPIISTA
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ADuC7124
SPIRX Register
Name: Address: Default Value: Access: Function: SPIRX 0xFFFF0A04 0x00 Read only This 8-bit MMR is the SPI receive register.
SPIDIV Register
Name: Address: Default Value: Access: Function: SPIDIV 0xFFFF0A0C 0x00 Write only This 8-bit MMR is the SPI baud rate selection register.
SPITX Register
Name: Address: Default Value: Access: Function: SPITX 0xFFFF0A08 0x00 Write only This 8-bit MMR is the SPI transmit register.
SPICON Register
Name: Address: Default Value: Access: Function: SPICON 0xFFFF0A10 0x0000 Read/write This 16-bit MMR configures the SPI peripheral in both master and slave modes.
Table 102. SPICON MMR Bit Designations
Bit 15:14 Name SPIMDE Description SPI IRQ mode bits. These bits configure when the Tx/Rx interrupts occur in a transfer. [00] = Tx interrupt occurs when one byte has been transferred. Rx interrupt occurs when one or more bytes have been received into the FIFO. [01] = Tx interrupt occurs when two bytes has been transferred. Rx interrupt occurs when two or more bytes have been received into the FIFO. [10] = Tx interrupt occurs when three bytes has been transferred. Rx interrupt occurs when three or more bytes have been received into the FIFO. [11] = Tx interrupt occurs when four bytes has been transferred. Rx interrupt occurs when the Rx FIFO is full or four bytes are present. SPI Tx FIFO flush enable bit. Set this bit to flush the Tx FIFO. This bit does not clear itself and should be toggled if a single flush is required. If this bit is left high, then either the last transmitted value or 0x00 is transmitted, depending on the SPIZEN bit. Any writes to the Tx FIFO are ignored while this bit is set. Clear this bit to disable Tx FIFO flushing. SPI Rx FIFO flush enable bit. Set this bit to flush the Rx FIFO. This bit does not clear itself and should be toggled if a single flush is required. If this bit is set incoming, data is ignored and no interrupts are generated. If set and SPITMDE = 0, a read of the Rx FIFO initiates a transfer. Clear this bit to disable Rx FIFO flushing. Continuous transfer enable. Set by the user to enable continuous transfer. In master mode, the transfer continues until no valid data is available in the Tx register. CS is asserted and remains asserted for the duration of each 8-bit serial transfer until Tx is empty. Cleared by the user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data exists in the SPITX register, then a new transfer is initiated after a stall period of one serial clock cycle. Loop back enable bit. Set by the user to connect MISO to MOSI and test software. Cleared by the user to be in normal mode. Slave MISO output enable bit. Set this bit for MISO to operate as normal. Clear this bit to disable the output driver on the MISO pin. The MISO pin is open-drain when this bit is cleared.
Rev. 0 | Page 61 of 96
13
SPITFLH
12
SPIRFLH
11
SPICONT
10
SPILP
9
SPIOEN
ADuC7124
Bit 8 Name SPIROW Description SPIRX overflow overwrite enable. Set by the user, the valid data in the Rx register is overwritten by the new serial byte received. Cleared by the user, the new serial byte received is discarded. SPI transmit zeros when Tx FIFO is empty. Set this bit to transmit 0x00 when there is no valid data in the Tx FIFO. Clear this bit to transmit the last transmitted value when there is no valid data in the Tx FIFO. SPI transfer and interrupt mode. Set by the user to initiate transfer with a write to the SPITX register. Interrupt occurs only when Tx is empty. Cleared by the user to initiate transfer with a read of the SPIRX register. Interrupt occurs only when Rx is full. LSB first transfer enable bit. Set by the user, the LSB is transmitted first. Cleared by the user, the MSB is transmitted first. SPI wired or mode enable bit. Set to 1 enable open drain data output. External pull-ups required on data out pins. Cleared for normal output levels. Serial clock polarity mode bit. Set by the user, the serial clock idles high. Cleared by the user, the serial clock idles low. Serial clock phase mode bit. Set by the user, the serial clock pulses at the beginning of each serial bit transfer. Cleared by the user, the serial clock pulses at the end of each serial bit transfer. Master mode enable bit. Set by the user to enable master mode. Cleared by the user to enable slave mode. SPI enable bit. Set by the user to enable the SPI. Cleared by the user to disable the SPI.
7
SPIZEN
6
SPITMDE
5
SPILF
4
SPIWOM
3
SPICPO
2
SPICPH
1
SPIMEN
0
SPIEN
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ADuC7124
I2C
The ADuC7124 incorporates two I2C peripherals that can be configured as a fully I2C compatible I2C bus master device or, as a fully I2C bus compatible slave device. Both I2C channels are identical. Therefore, the following descriptions apply to both channels. The two pins used for data transfer, SDA and SCL, are configured in a wired AND format that allows arbitration in a multimaster system. These pins require external pull-up resistors. Typical pull-up values are between 4.7 k and 10 k. The I2C bus peripheral address in the I2C bus system is programmed by the user. This ID can be modified any time a transfer is not in progress. The user can configure the interface to respond to four slave addresses. The transfer sequence of an I2C system consists of a master device initiating a transfer by generating a start condition while the bus is idle. The master transmits the slave device address and the direction of the data transfer (read or/write) during the initial address transfer. If the master does not lose arbitration and the slave acknowledges, the data transfer is initiated. This continues until the master issues a stop condition and the bus becomes idle. The I2C peripheral can only be configured as a master or slave at any given time. The same I2C channel cannot simultaneously support master and slave modes. The I2C interface on the ADuC7124 includes the following features: * Support for repeated start conditions. In master mode, the ADuC7124 can be programmed to generate a repeated start. In slave mode, the ADuC7124 recognizes repeated start conditions. In master and slave mode, the part recognizes both 7-bit and 10-bit bus addresses. In I2C master mode, the ADuC7124 supports continuous reads from a single slave up to 512 bytes in a single transfer sequence. Clock stretching is supported in both master and slave modes. In slave mode, the ADuC7124 can be programmed to return a NACK. This allows the validiation of checksum bytes at the end of I2C transfers. Bus arbitration in master mode is supported. Internal and external loopback modes are supported for I2C hardware testing in loopback mode. The transmit and receive circuits in both master and slave mode contain 2-byte FIFOs. Status bits are available to the user to control these FIFOs.
Configuring External Pins for I2C Functionality
The I2C pins of the ADuC7124 device are P1.0 and P1.1 for I2C0 and P1.2 and P1.3 for I2C1. P1.0 and P1.2 are the I2C clock signals, and P1.1 and P1.3 are the I2C data signals. For instance, to configure I2C0 pins (SCL0, SDA0), Bit 0 and Bit 4 of the GP1CON register must be set to 1 to enable I2C mode. On the other hand, to configure I2C1 pins (SCL1, SDA1), Bit 8 and Bit 12 of the GP1CON register must be set to 1 to enable I2C mode, as shown in the GeneralPurpose Input/Output section.
Serial Clock Generation
The I2C master in the system generates the serial clock for a transfer. The master channel can be configured to operate in fast mode (400 kHz) or standard mode (100 kHz). The bit rate is defined in the I2CxDIV MMR as follows:
f SERIAL CLOCK = fUCLK (2 + DIVH ) + (2 + DIVL)
where: fUCLK is the clock before the clock divider. DIVH is the high period of the clock. DIVL is the low period of the clock. Therefore, for 100 kHz operation, DIVH = DIVL = 0xCF and for 400 kHz DIVH = 0x28, DIVL = 0x3C The I2CxDIV register corresponds to DIVH:DIVL.
I2C Bus Addresses Slave Mode
In slave mode, the I2CxID0, I2CxID1, I2CxID2, and I2CxID3 registers contain the device IDs. The device compares the four I2CxIDx registers to the address byte received from the bus master. To be correctly addressed, the seven MSBs of either ID register must be identical to seven MSBs of the first received address byte. The LSB of the ID registers (the transfer direction bit) is ignored in the process of address recognition. The ADuC7124 also supports 10-bit addressing mode. When Bit 1 of I2CxSCON (ADR10EN bit) is set to 1, one 10-bit address is supported in slave mode and is stored in the I2CxID0 and I2CxID1 registers. The 10-bit address is derived as follows: I2CxID0[0] is the read/write bit and is not part of the I2C address. I2CxID0[7:1] = Address Bits[6:0]. I2CxID1[2:0] = Address Bits[9:7]. I2CxID1[7:3] must be set to 11110b.
* *
* *
* * *
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ADuC7124
Master Mode
In master mode, the I2CxADR0 register is programmed with the I2C address of the device. In 7-bit address mode, I2CxADR0[7:1] are set to the device address. I2CxADR0[0] is the read/write bit. In 10-bit address mode, the 10-bit address is created as follows: I2CxADR0[7:3] must be set to 11110b. I2CxADR0[2:1] = Address Bits[9:8]. I2CxADR1[7:0] = Address Bits[7:0]. I2CxADR0[0] is the read/write bit.
I2C Master Registers I2C Master Control Register
Name: Address: Default Value: Access: Function: I2C0MCON, I2C1MCON 0xFFFF0800, 0xFFFF0900 0x0000, 0x0000 Read/write This 16-bit MMR configures the I2C peripheral in master mode.
I2C Registers
The I2C peripheral interfaces consists of a number of MMRs. These are described in the I2C Master Registers section. Table 103. I2CxMCON MMR Bit Designations
Bit 15:9 8 Name I2CMCENI Description Reserved. These bits are reserved and should not be written to. I2C transmission complete interrupt enable bit. Set this bit to enable an interrupt on detecting a stop condition on the I2C bus. Clear this bit to clear the interrupt source. I2C NACK received interrupt enable bit. Set this bit to enable interrupts when the I2C master receives a NACK. Clear this bit to clear the interrupt source. I2C arbitration lost interrupt enable bit. Set this bit to enable interrupts when the I2C master is unable to gain control of the I2C bus. Clear this bit to clear the interrupt source. I2C transmit interrupt enable bit. Set this bit to enable interrupts when the I2C master has transmitted a byte. Clear this bit to clear the interrupt source. I2C receive interrupt enable bit. Set this bit to enable interrupts when the I2C master receives data. Cleared by user to disable interrupts when the I2C master is receiving data. I2C master SCL stretch enable bit. Set this bit to 1 to enable clock stretching. When SCL is low, setting this bit forces the device to hold SCL low until I2CMSEN is cleared. If SCL is high, setting this bit forces the device to hold SCL low after the next falling edge. Clear this bit to disable clock stretching. I2C internal loopback enable. Set this bit to enable loopback test mode. In this mode, the SCL and SDA signals are connected internally to their respective input signals. Cleared by the user to disable loopback mode. I2C master backoff disable bit Set this bit to allow the device to compete for control of the bus even if another device is currently driving a start condition. Clear this bit to wait until the I2C bus becomes free. I2C master enable bit. Set by the user to enable I2C master mode. Clear this bit to disable I2C master mode.
7
I2CNACKENI
6
I2CALENI
5
I2CMTENI
4
I2CMRENI
3
I2CMSEN
2
I2CILEN
1
I2CBD
0
I2CMEN
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ADuC7124
I2C Master Status Register
Name: Address: Default Value: Access: Function: I2C0MSTA, I2C1MSTA 0xFFFF0804, 0xFFFF0904 0x0000, 0x0000 Read only This 16-bit MMR is the I2C status register in master mode.
Table 104 I2CxMSTA MMR Bit Designations
Bit 15:11 10 Name I2CBBUSY Description Reserved. These bits are reserved. I2C bus busy status bit. This bit is set to 1 when a start condition is detected on the I2C bus. This bit is cleared when a stop condition is detected on the bus. Master Rx FIFO overflow. This bit is set to 1 when a byte is written to the Rx FIFO when it is already full. This bit is cleared in all other conditions. I2C transmission complete status bit. This bit is set to 1 when a transmission is complete between the master and the slave it was communicating with. If the I2CMCENI bit in I2CxMCON is set, an interrupt is generated when this bit is set. Clear this bit to clear the interrupt source. I2C master NACK data bit. This bit is set to 1 when a NACK condition is received by the master in response to a data write transfer. If the I2CNACKENI bit in I2CxMCON is set, an interrupt is generated when this bit is set. This bit is cleared in all other conditions. I2C master busy status bit. Set to 1 when the master is busy processing a transaction. Cleared if the master is ready or if another master device has control of the bus. I2C arbitration lost status bit. This bit is set to 1 when the I2C master is unable to gain control of the I2C bus. If the I2CALENI bit in I2CxMCON is set, an interrupt is generated when this bit is set. This bit is cleared in all other conditions. I2C master NACK address bit. This bit is set to 1 when a NACK condition is received by the master in response to an address. If the I2CNACKENI bit in I2CxMCON is set, an interrupt is generated when this bit is set. This bit is cleared in all other conditions. I2C master receive request bit. This bit is set to 1 when data enters the Rx FIFO. If the I2CMRENI in I2CxMCON is set, an interrupt is generated. This bit is cleared in all other conditions. I2C master transmit request bit. This bit goes high if the Tx FIFO is empty or contains only one byte and the master has transmitted an Address + write. If the I2CMTENI bit in I2CxMCON is set, an interrupt is generated when this bit is set. This bit is cleared in all other conditions. I2C master Tx FIFO status bits. 00 = I2C master Tx FIFO empty. 01 = one byte in master Tx FIFO. 10 = one byte in master Tx FIFO. 11 = I2C master Tx FIFO full.
9
I2CMRxFO
8
I2CMTC
7
I2CMNA
6
I2CMBUSY
5
I2CAL
4
I2CMNA
3
I2CMRXQ
2
I2CMTXQ
1-0
I2CMTFSTA
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ADuC7124
I2C Master Receive Register
Name: Address: Default Value: Access: Function: I2C0MRX, I2C1MRX 0xFFFF0808, 0xFFFF0908 0x00 Read only This 8-bit MMR is the I2C master receive register.
I2C Master Current Read Count Register
Name: Address: Default Value: Access: Function: I2C0MCNT1, I2C1MCNT1 0xFFFF0814, 0xFFFF0914 0x00, 0x00 Read only This 8-bit MMR holds the number of bytes received so far during a read sequence with a slave device.
I2C Master Transmit Register
Name: Address: Default Value: Access: Function: I2C0MTX, I2C1MTX 0xFFFF080C 0xFFFF090C 0x00, 0x00 Write only This 8-bit MMR is the I2C master transmit register.
I2C Address 0 Register
Name: Address: Default Value: Access: Function: I2C0ADR0, I2C1ADR0 0xFFFF0818, 0xFFFF0918 0x00 Read/write This 8-bit MMR holds the 7-bit slave address + the read/write bit when the master begins communicating with a slave.
I2C Master Read Count Register
Name: Address: Default Value: Access: Function: I2C0MCNT0, I2C1MCNT0 0xFFFF0810, 0xFFFF0910 0x0000, 0x0000 Read/write This 16-bit MMR holds the required number of bytes when the master begins a read sequence from a slave device.
Table 106. I2CxADR0 MMR in 7-Bit Address Mode (Address = 0xFFFF0818, 0xFFFF0918. Default Value = 0x00)
Bit 7:1 0 Name I2CADR R/W Description These bits contain the 7-bit address of the required slave device. Bit 0 is the read/write bit. When this bit = 1, a read sequence is requested. When this bit = 0, a write sequence is requested.
Table 105. I2CxMCNT0 MMR Bit Descriptions (Address = 0xFFFF0810, 0xFFFF0910. Default Value = 0x0000)
Bit 15:9 8 Name I2CRECNT Description Reserved. Set this bit if greater than 256 bytes are required from the slave. Clear this bit when reading 256 bytes or less. These eight bits hold the number of bytes required during a slave read sequence, minus 1. If only a single byte is required, these bits should be set to 0.
Table 107. I2CxADR0 MMR in 10-Bit Address Mode
Bit 7:3 2:1 0 Name Description These bits must be set to [11110b] in 10-bit address mode. These bits contain ADDR[9:8] in 10-bit addressing mode. Read/write bit. When this bit = 1, a read sequence is requested. When this bit = 0, a write sequence is requested.
I2CMADR R/W
7:0
I2CRCNT
I2C Address 1 Register
Name: Address: Default Value: Access: Function: I2C0ADR1, I2C1ADR1 0xFFFF081C, 0xFFFF091C 0x00 Read/write This 8-bit MMR is used in 10-bit addressing mode only. This register contains the least significant byte of the address.
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ADuC7124
Table 108. I2CxADR1 MMR in 10-Bit Address Mode
Bit 7:0 Name I2CLADR Description These bits contain ADDR[7:0] in 10-bit addressing mode.
Table 109. I2CxDIV MMR
Bit 15:8 7:0 Name DIVH DIVL Description These bits control the duration of the high period of SCL. These bits control the duration of the low period of SCL.
I2C Master Clock Control Register
Name: Address: Default Value: Access: Function: I2C0DIV, I2C1DIV 0xFFFF0824, 0xFFFF0924 0x1F1F Read/write This MMR controls the frequency of the I2C clock generated by the master on to the SCL pin. For further details, see the I2C section.
I2C Slave Registers I2C Slave Control Register
Name: Address: Default value: Access: Function: I2C0SCON, I2C1SCON 0xFFFF0828, 0xFFFF0928 0x0000 Read/write This 16-bit MMR configures the I2C peripheral in slave mode.
Table 110. I2CxSCON MMR Bit Designations
Bit 15:11 10 Name I2CSTXENI Description Reserved bits. Slave transmit interrupt enable bit. Set this bit to enable an interrupt after a slave transmits a byte. Clear this interrupt source. Slave receive interrupt enable bit. Set this bit to enable an interrupt after the slave receives data. Clear this interrupt source. I2C stop condition detected interrupt enable bit. Set this bit to enable an interrupt on detecting a stop condition on the I2C bus. Clear this interrupt source. I2C NACK enable bit. Set this bit to NACK the next byte in the transmission sequence. Clear this bit to let the hardware control the ACK/NACK sequence. I2C slave SCL stretch enable bit. Set this bit to 1 to enable clock stretching. When SCL is low, setting this bit forces the device to hold SCL low until I2CSSEN is cleared. If SCL is high, setting this bit forces the device to hold SCL low after the next falling edge. Clear this bit to disable clock stretching. I2C early transmit interrupt enable bit. Setting this bit enables a transmit request interrupt just after the positive edge of SCL during the read bit transmission. Clear this bit to enable a transmit request interrupt just after the negative edge of SCL during the read bit transmission. I2C general call status and ID clear bit. Writing a 1 to this bit clears the general call status and ID bits in the I2CxSSTA register. Clear this bit at all other times.
9
I2CSRXENI
8
I2CSSENI
7
I2CNACKEN
6
I2CSSEN
5
I2CSETEN
4
I2CGCCLR
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ADuC7124
Bit 3 Name I2CHGCEN Description I2C hardware general call enable. When this bit and Bit 2 are set, and having received a general call (Address 0x00) and a data byte, the device checks the contents of the I2CxALT against the receive register. If the contents match, the device has received a hardware general call. This is used if a device needs urgent attention from a master device without knowing which master it needs to turn to. This is a "to whom it may concern" call. The ADuC7124 watches for these addresses. The device that requires attention embeds its own address into the message. All masters listen, and the one that can handle the device contacts its slave and acts appropriately. The LSB of the I2CxALT register should always be written to 1, as per the I2C January 2000 bus specification. Set this bit and I2CGCEN to enable hardware general call recognition in slave mode. Clear this bit to disable recognition of hardware general call commands. I2C general call enable. Set this bit to enable the slave device to acknowledge an I2C general call, Address 0x00 (write). The device then recognizes a data bit. If it receives a 0x06 (reset and write programmable part of the slave address by hardware) as the data byte, the I2C interface resets as per the I2C January 2000 bus specification. This command can be used to reset an entire I2C system. If it receives a 0x04 (write programmable part of the slave address by hardware) as the data byte, the general call interrupt status bit sets on any general call. The user must take corrective action by reprogramming the device address. Set this bit to allow the slave ACK I2C general call commands. Clear this bit to disable recognition of general call commands. I2C 10-bit address mode. Set to 1 to enable 10-bit address mode. Clear to 0 to enable normal address mode. I2C slave enable bit. Set by the user to enable I2C slave mode. Clear this bit to disable I2C slave mode.
2
I2CGCEN
1
ADR10EN
0
I2CSEN
I2C Slave Status Registers
Name: Address: Default Value: Access: Function: I2C0SSTA, I2C1SSTA 0xFFFF082C, 0xFFFF092C 0x0000, 0x0000 Read/write This 16-bit MMR is the I2C status register in slave mode.
Table 111. I2CxSSTA MMR Bit Designations
Bit 15 14 Name I2CSTA Description Reserved bit. This bit is set to 1 if: * A start condition followed by a matching address is detected. * A start byte (0x01) is received. * General calls are enabled and a general call code of (0x00) is received. This bit is cleared on receiving a stop condition. This bit is set to 1 if a repeated start condition is detected. This bit is cleared on receiving a stop condition. I2C address matching register. These bits indicate which I2CxIDx register matches the received address. [00] = received address matches I2CxID0. [01] = received address matches I2CxID1. [10] = received address matches I2CxID2. [11] = received address matches I2CxID3. I2C stop condition after start detected bit. This bit is set to 1 when a stop condition is detected after a previous start and matching address. When the I2CSSENI bit in I2CxSCON is set, an interrupt is generated. This bit is cleared by reading this register.
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13 12:11
I2CREPS I2CID[1:0]
10
I2CSS
ADuC7124
Bit 9:8 Name I2CGCID[1:0] Description I2C general call ID bits. [00] = no general call received. [01] = general call reset and program address. [10] = general program address. [11] = general call matching alternative ID. Note that these bits are not cleared by a general call reset command. Clear these bits by writing a 1 to the I2CGCCLR bit in I2CxSCON. I2C general call status bit. This bit is set to 1 if the slave receives a general call command of any type. If the command received is a reset command, then all registers return to their default states. If the command received is a hardware general call, the Rx FIFO holds the second byte of the command and this can be compared with the I2CxALT register. Clear this bit by writing a 1 to the I2CGCCLR bit in I2CxSCON. I2C slave busy status bit. Set to 1 when the slave receives a start condition. Cleared by hardware if * The received address does not match any of the I2CxIDx registers. * The slave device receives a stop condition. * A repeated start address doesn't match any of the I2CxIDx registers. I2C slave NACK data bit. This bit is set to 1 when the slave responds to a bus address with a NACK. This bit is asserted under the following conditions: * INACK was returned because there was no data in the Tx FIFO. * The I2CNACKEN bit was set in the I2CxSCON register. This bit is cleared in all other conditions. Slave Rx FIFO overflow. This bit is set to 1 when a byte is written to the Rx FIFO when it is already full. This bit is cleared in all other conditions. I2C slave receive request bit. This bit is set to 1 when the slave Rx FIFO is not empty. This bit causes an interrupt to occur when the I2CSRXENI bit in I2CxSCON is set. The Rx FIFO must be read or flushed to clear this bit. I2C slave transmit request bit. This bit is set to 1 when the slave receives a matching address followed by a read. If the I2CSETEN bit in I2CxSCON is = 0, this bit goes high just after the negative edge of SCL during the read bit transmission. If the I2CSETEN bit in I2CxSCON is = 1, this bit goes high just after the positive edge of SCL during the read bit transmission. This bit causes an interrupt to occur when the I2CSTXENI bit in I2CxSCON is set. This bit is cleared in all other conditions. I2C slave FIFO underflow status bit. This bit goes high if the Tx FIFO is empty when a master requests data from the slave. This bit is asserted at the rising edge of SCL during the read bit. This bit is cleared in all other conditions. I2C slave early transmit FIFO status bit. If the I2CSETEN bit in I2CxSCON is = 0, this bit goes high if the slave Tx FIFO is empty. If the I2CSETEN bit in I2CxSCON is = 1, this bit goes high just after the positive edge of SCL during the write bit transmission. This bit asserts once only for a transfer. This bit is cleared after being read.
7
I2CGC
6
I2CSBUSY
5
I2CSNA
4
I2CSRxFO
3
I2CSRXQ
2
I2CSTXQ
1
I2CSTFE
0
I2CETSTA
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ADuC7124
I2C Slave Receive Registers
Name: Address: Default Value: Access: Function: I2C0SRX, I2C1SRX 0xFFFF0830, 0xFFFF0930 0x00 Read This 8-bit MMR is the I2C slave receive register.
I2C Common Registers I2C FIFO Status Register
Name: Address: Default Value: Access: Function: I2C0FSTA, I2C1FSTA 0xFFFF084C, 0xFFFF094C 0x0000 Read/write These 16-bit MMRs contain the status of the Rx/Tx FIFOs in both master and slave modes.
I2C Slave Transmit Registers
Name: Address: Default Value: Access: Function: I2C0STX, I2C1STX 0xFFFF0834, 0xFFFF0934 0x00 Write This 8-bit MMR is the I2C slave transmit register.
Table 112. I2CxFSTA MMR Bit Designations
Bit 15:10 9 8 7:6 Name I2CFMTX I2CFSTX I2CMRXSTA Description Reserved bits. Set this bit to 1 to flush the master Tx FIFO. Set this bit to 1 to flush the slave Tx FIFO. I2C master receive FIFO status bits. [00] = FIFO empty. [01] = byte written to FIFO. [10] = one byte in FIFO. [11] = FIFO full. I2C master transmit FIFO status bits. [00] = FIFO empty. [01] = byte written to FIFO. [10] = one byte in FIFO. [11] = FIFO full. I2C slave receive FIFO status bits. [00] = FIFO empty. [01] = byte written to FIFO. [10] = one byte in FIFO. [11] = FIFO full. I2C slave transmit FIFO status bits. [00] = FIFO empty. [01] = byte written to FIFO. [10] = one byte in FIFO. [11] = FIFO full.
I2C Hardware General Call Recognition Registers
Name: Address: Default Value: Access: Function: I2C0ALT, I2C1ALT 0xFFFF0838, 0xFFFF0938 0x00 Read/write This 8-bit MMR is used with hardware general calls when the I2CxSCON Bit 3 is set to 1. This register is used in cases where a master is unable to generate an address for a slave, and instead, the slave must generate the address for the master.
3:2 I2CSRXSTA 5:4 I2CMTXSTA
I2C Slave Device ID Registers
Name: Addresses: I2C0IDx, I2C1IDx 0xFFFF093C = I2C1ID0 0xFFFF083C = I2C0ID0 0xFFFF0940 = I2C1ID1 0xFFFF0840 = I2C0ID1 0xFFFF0944 = I2C1ID2 0xFFFF0844 = I2C0ID2 0xFFFF0948 = I2C1ID3 0xFFFF0848 = I2C0ID3 Default Value: Access: Function: 0x00 Read/write These 8-bit MMRs are programmed with I2C bus IDs of the slave. See the I2C Bus Addresses section for further details.
1:0
I2CSTXSTA
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ADuC7124
PWM GENERAL OVERVIEW
The ADuC7124 integrates a six channel PWM interface (PWM0 to PWM5). The PWM outputs can be configured to drive an H-bridge or can be used as standard PWM outputs. On power-up, the PWM outputs default to H-bridge mode. This ensures that the motor is turned off by default. In standard PWM mode, the outputs are arranged as three pairs of PWM pins. The user has control over the period of each pair of outputs and over the duty cycle of each individual output. Table 113. PWM MMRs
Name PWMCON0 PWM0COM0 PWM0COM1 PWM0COM2 PWM0LEN PWM1COM0 PWM1COM1 PWM1COM2 PWM1LEN PWM2COM0 PWM2COM1 PWM2COM2 PWM2LEN PWMCON1 PWMCLRI Function PWM control. Compare Register 0 for PWM Output 0 and PWM Output 1. Compare Register 1 for PWM Output 0 and PWM Output 1. Compare Register 2 for PWM Output 0 and PWM Output 1. Frequency control for PWM Output 0 and PWM Output 1. Compare Register 0 for PWM Output 2 and PWM Output 3. Compare Register 1 for PWM Output 2 and PWM Output 3. Compare Register 2 for PWM Output 2 and PWM Output 3. Frequency control for PWM Output 2 and PWM Output 3. Compare Register 0 for PWM Output 4 and Output 5 Compare Register 1 for PWM Outputs 4 and Output 5 Compare Register 2 for PWM Outputs 4 and Output 5 Frequency control for PWM Output 4 and PWM Output 5. PWM control register PWM interrupt clear.
In all modes, the PWMxCOMx MMRs control the point at which the PWM outputs change state. An example of the first pair of PWM outputs (PWM0 and PWM1) is shown in Figure 48.
HIGH SIDE (PWM0)
LOW SIDE (PWM1)
PWM0COM2 PWM0COM1 PWM0COM0 PWM0LEN
09123-120
Figure 48. PWM Timing
The PWM clock is selectable via PWMCON with one of the following values: UCLK divided by 2, 4, 8, 16, 32, 64, 128, or 256. The length of a PWM period is defined by PWMxLEN. The PWM waveforms are set by the count value of the 16-bit timer and the compare registers contents, as shown with the PWM0 and PWM1 waveforms in Figure 48. The low-side waveform, PWM1, goes high when the timer count reaches PWM0LEN, and it goes low when the timer count reaches the value held in PWM0COM2 or when the high-side waveform (PWM0) goes low. The high-side waveform, PWM0, goes high when the timer count reaches the value held in PWM0COM0, and it goes low when the timer count reaches the value held in PWM0COM1.
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ADuC7124
Table 114. PWMCON0 PWMCON MMR Bit Designations
Bit 14 Name SYNC Description Enables PWM synchronization. Set to 1 by the user so that all PWM counters are reset on the next clock edge after the detection of a high-to-low transition on the P3.7/PWMSYNC pin. Cleared by the user to ignore transitions on the P3.7/PWMSYNC pin. Set to 1 by the user to invert PWM5. Cleared by the user to use PWM5 in normal mode. Set to 1 by the user to invert PWM3. Cleared by the user to use PWM3 in normal mode. Set to 1 by the user to invert PWM1. Cleared by the user to use PWM1 in normal mode. Set to 1 by the user to enable PWM trip interrupt. When the PWM trip input (Pin P3.6/PWMTRIPINPUT) is low, the PWMEN bit is cleared and an interrupt is generated. Cleared by the user to disable the PWMTRIP interrupt. If HOFF = 0 and HMODE = 1; note that, if not in H-bridge mode, this bit has no effect. Set to 1 by the user to enable PWM outputs. Cleared by the user to disable PWM outputs. If HOFF = 1 and HMODE = 1, see Table 115. PWM clock prescaler bits. Sets the UCLK divider. [000] = UCLK/2. [001] = UCLK/4. [010] = UCLK/8. [011] = UCLK/16. [100] = UCLK/32. [101] = UCLK/64. [110] = UCLK/128. [111] = UCLK/256. Set to 1 by the user to invert all PWM outputs. Cleared by the user to use PWM outputs as normal. High side off. Set to 1 by the user to force PWM0 and PWM2 outputs high. This also forces PWM1 and PWM3 low. Cleared by the user to use the PWM outputs as normal. Load compare registers. Set to 1 by the user to load the internal compare registers with the values in PWMxCOMx on the next transition of the PWM timer from 0x00 to 0x01. Cleared by the user to use the values previously stored in the internal compare registers. Direction control. Set to 1 by the user to enable PWM0 and PWM1 as the output signals while PWM2 and PWM3 are held low. Cleared by the user to enable PWM2 and PWM3 as the output signals while PWM0 and PWM1 are held low. Enables H-bridge mode.1 Set to 1 by the user to enable H-bridge mode and Bit 1 to Bit 5 of PWMCON. Cleared by the user to operate the PWMs in standard mode. Set to 1 by the user to enable all PWM outputs. Cleared by the user to disable all PWM outputs.
13 12 11 10
PWM5INV PWM3INV PWM1INV PWMTRIP
9
ENA
8 to 6
PWMCP[2:0]
5 4
POINV HOFF
3
LCOMP
2
DIR
1
HMODE
0
1
PWMEN
In H-bridge mode, HMODE = 1. See Table 115 to determine the PWM outputs.
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ADuC7124
Table 115. PWM Output Selection
ENA 0 X 1 1 1 1
1 2
PWMCON0 MMR HOFF POINV 0 X 1 X 0 0 0 0 0 1 0 1
1
DIR X X 0 1 0 1
PWM0 1 1 0 HS HS 1
PWM Outputs PWM1 PWM2 1 1 0 1 0 HS LS 0 LS 1 1 HS
2
Table 117. PWMCON1 MMR Bit Designations (Address = 0xFFFF0FB4. Default Value = 0x00)
PWM3 1 0 LS 0 1 LS
Bit 7
Value
Name CSEN
3:0
CSD3 CSD2 CSD1 CSD0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Description Set to 1 by the user to enable the PWM to generate a convert start signal. Cleared by user to disable the PWM convert start signal. Convert start delay. Delays the convert start signal by a number of clock pulses.
X = don't care. HS = high side, LS = low side.
On power-up, PWMCON0 defaults to 0x12 (HOFF = 1 and HMODE = 1). All GPIO pins associated with the PWM are configured in PWM mode by default (see Table 116). Table 116. Compare Registers
Name PWM0COM0 PWM0COM1 PWM0COM2 PWM1COM0 PWM1COM1 PWM1COM2 PWM2COM0 PWM2COM1 PWM2COM2 Address 0xFFFF0F84 0xFFFF0F88 0xFFFF0F8C 0xFFFF0F94 0xFFFF0F98 0xFFFF0F9C 0xFFFF0FA4 0xFFFF0FA8 0xFFFF0FAC Default Value 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W
The PWM trip interrupt can be cleared by writing any value to the PWMCLRI MMR. Note that, when using the PWM trip interrupt, users should make sure that the PWM interrupt has been cleared before exiting the ISR. This prevents generation of multiple interrupts.
Four clock pulses. Eight clock pulses. 12 clock pulses. 16 clock pulses. 20 clock pulses. 24 clock pulses. 28 clock pulses. 32 clock pulses. 36 clock pulses. 40 clock pulses. 44 clock pulses. 48 clock pulses. 52 clock pulses. 56 clock pulses. 60 clock pulses. 64 clock pulses.
PWM Convert Start Control
The PWM can be configured to generate an ADC convert start signal after the active low side signal goes high. There is a programmable delay between the time that the low-side signal goes high and the convert start signal is generated. This is controlled via the PWMCON1 MMR. If the delay selected is higher than the width of the PWM pulse, the interrupt remains low.
When calculating the time from the convert start delay to the start of an ADC conversion, the user must to take account of internal delays. The example below shows the case for a delay of four clocks. One additional clock is required to pass the convert start signal to the ADC logic. Once the ADC logic receives the convert start signal, an ADC conversion begins on the next ADC clock edge (see Figure 49).
UCLOCK
LOW SIDE
COUNT
PWM SIGNAL TO CONVST SIGNAL PASSED TO ADC LOGIC
09123-045
Figure 49. ADC Conversion
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ADuC7124
PROGRAMMABLE LOGIC ARRAY (PLA)
Every ADuC7124 integrates a fully programmable logic array (PLA) that consists of two independent but interconnected PLA blocks. Each block consists of eight PLA elements, giving each part a total of 16 PLA elements. Each PLA element contains a two-input look up table that can be configured to generate any logic output function based on two inputs and a flip-flop. This is represented in Figure 50.
0 2 A LOOK-UP TABLE 3 1
09123-133
PLAELMx Registers
Name PLAELM0 PLAELM1 PLAELM2 PLAELM3 PLAELM4 PLAELM5 PLAELM6 PLAELM7 PLAELM8 PLAELM9 PLAELM10 PLAELM11 PLAELM12 PLAELM13 PLAELM14 PLAELM15 Address 0xFFFF0B00 0xFFFF0B04 0xFFFF0B08 0xFFFF0B0C 0xFFFF0B10 0xFFFF0B14 0xFFFF0B18 0xFFFF0B1C 0xFFFF0B20 0xFFFF0B24 0xFFFF0B28 0xFFFF0B2C 0xFFFF0B30 0xFFFF0B34 0xFFFF0B38 0xFFFF0B3C Default Value 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
4
B
Figure 50. PLA Element
In total, 32 GPIO pins are available on the ADuC7124 for the PLA. These include 16 input pins and 16 output pins, which must to be configured in the GPxCON register as PLA pins before using the PLA. Note that the comparator output is also included as one of the 16 input pins. The PLA is configured via a set of user MMRs. The output(s) of the PLA can be routed to the internal interrupt system, to the CONVSTART signal of the ADC, to an MMR, or to any of the 16 PLA output pins. The two blocks can be interconnected as follows: Output of Element 15 (Block 1) can be fed back to Input 0 of Mux 0 of Element 0 (Block 0). Output of Element 7 (Block 0) can be fed back to Input 0 of Mux 0 of Element 8 (Block 1).
The PLAELMx are Element 0 to Element 15 control registers. They configure the input and output mux of each element, select the function in the look up table, and bypass/use the flipflop (see Table 119 and Table 122). Table 119. PLAELMx MMR Bit Descriptions
Bit 31:11 10:9 8:7 6 Value Description Reserved. Mux 0 control (see Table 122). Mux 1 control (see Table 122). Mux 2 control. Set by the user to select the output of Mux 0. Cleared by the user to select the bit value from PLADIN. Mux 3 control. Set by the user to select the input pin of the particular element. Cleared by the user to select the output of Mux 1. Look up table control. 0. NOR. B AND NOT A. NOT A. A AND NOT B. NOT B. EXOR. NAND. AND. EXNOR. B. NOT A OR B. A. A OR NOT B. OR. 1. Mux 4 control. Set by the user to bypass the flip-flop. Cleared by the user to select the flip-flop (cleared by default).
5
Table 118. Element Input/Output1
PLA Block 0 Element Input 0 P1.0 1 P1.1 2 P1.2 3 P1.3 4 P1.4 5 P1.5 6 P1.6 7 P0.0
1
4:1 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0
Output P1.7 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2
PLA Block 1 Element Input 8 P3.0 9 P3.1 10 P3.2 11 P3.3 12 P3.4 13 P3.5 14 P3.6 15 P3.7
Output P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7
Not all pins in this table are connected to external pins. However, they may be routed internally via the PLA. See Table 122 for further details.
PLA MMRs Interface
The PLA peripheral interface consists of the 22 MMRs.
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ADuC7124
PLACLK Register
Name: Address: Default Value: Access: PLACLK 0xFFFF0B40 0x00 Read/write
PLAIRQ Register
Name: Address: Default Value: Access: PLAIRQ 0xFFFF0B44 0x00000000 Read/write
PLACLK is the clock selection for the flip-flops of Block 0 and Block 1. Note that the maximum frequency when using the GPIO pins as the clock input for the PLA blocks is 41.78 MHz. Table 120. PLACLK MMR Bit Descriptions
Bit 7 6:4 Value Description Reserved. Block 1 clock source selection. GPIO clock on P0.5. GPIO clock on P0.0. GPIO clock on P0.7. HCLK. OCLK (32.768 kHz). Timer1 overflow. UCLK. Internal 32,768 oscillator. Reserved. Block 0 clock source selection. GPIO clock on P0.5. GPIO clock on P0.0. GPIO clock on P0.7. HCLK. OCLK (32.768 kHz). Timer1 overflow. Reserved.
PLAIRQ enables IRQ0 and/or IRQ1 and selects the source of the IRQ. Table 121. PLAIRQ MMR Bit Descriptions
Bit 15:13 12 Value Description Reserved. PLA IRQ1 enable bit. Set by the user to enable IRQ1 output from PLA. Cleared by the user to disable IRQ1 output from PLA. PLA IRQ1 source. PLA Element 0. PLA Element 1. PLA Element 15. Reserved. PLA IRQ0 enable bit. Set by the user to enable IRQ0 output from PLA. Cleared by the user to disable IRQ0 output from PLA. PLA IRQ0 source. PLA Element 0. PLA Element 1. PLA Element 15.
000 001 010 011 100 101 110 111 3 2:0 000 001 010 011 100 101 Other
11:8 0000 0001 1111 7:5 4
3:0 0000 0001 1111
Table 122. Feedback Configuration
Bit 10:9 Value 00 01 10 11 00 01 10 11 PLAELM0 Element 15 Element 2 Element 4 Element 6 Element 1 Element 3 Element 5 Element 7 PLAELM1 to PLAELM7 Element 0 Element 2 Element 4 Element 6 Element 1 Element 3 Element 5 Element 7 PLAELM8 Element 7 Element 10 Element 12 Element 14 Element 9 Element 11 Element 13 Element 15 PLAELM9 to PLAELM15 Element 8 Element 10 Element 12 Element 14 Element 9 Element 11 Element 13 Element 15
8:7
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ADuC7124
PLAADC Register
Name: Address: Default Value: Access: PLAADC 0xFFFF0B48 0x00000000 Read/write Table 124. PLADIN MMR Bit Descriptions
Bit 31:16 15:0 Description Reserved. Input bit to Element 15 to Element 0.
PLADOUT Register
Name: Address: Default Value: Access: PLADOUT 0xFFFF0B50 0x00000000 Read only
PLAADC is the PLA source for the ADC start conversion signal. Table 123. PLAADC MMR Bit Descriptions
Bit 31:5 4 Value Description Reserved. ADC start conversion enable bit. Set by the user to enable ADC start conversion from PLA. Cleared by the user to disable ADC start conversion from PLA. ADC start conversion source. PLA Element 0. PLA Element 1. PLA Element 15.
PLADOUT is a data output MMR for PLA. This register is always updated. Table 125. PLADOUT MMR Bit Descriptions
Bit 31:16 15:0 Description Reserved. Output bit from Element 15 to Element 0.
3:0 0000 0001 1111
PLALCK Register
Name: PLALCK 0xFFFF0B54 0x00 Write only Address: Default Value: Access:
PLADIN Register
Name: Address: Default Value: Access: PLADIN 0xFFFF0B4C 0x00000000 Read/write
PLADIN is a data input MMR for PLA.
PLALCK is a PLA lock option. Bit 0 is written only once. When set, it does not allow modification of any of the PLA MMRs, except PLADIN. A PLA tool is provided in the development system to easily configure the PLA.
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ADuC7124 PROCESSOR REFERENCE PERIPHERALS
INTERRUPT SYSTEM
There are 25 interrupt sources on the ADuC7124 that are controlled by the interrupt controller. All interrupts are generated from the on-chip peripherals, except for the software interrupt (SWI) which is programmable by the user. The ARM7TDMI CPU core recognizes interrupts as one of two types: a normal interrupt request (IRQ) and a fast interrupt request (FIQ). All the interrupts can be masked separately. The control and configuration of the interrupt system is managed through a number of interrupt-related registers. The bits in each IRQ and FIQ register represent the same interrupt source as described in Table 126. The ADuC7124 contains a vectored interrupt controller (VIC) that supports nested interrupts up to eight levels. The VIC also allows the programmer to assign priority levels to all interrupt sources. Interrupt nesting must be enabled by setting the ENIRQN bit in the IRQCONN register. A number of extra MMRs are used when the full-vectored interrupt controller is enabled. IRQSTA/FIQSTA should be saved immediately upon entering the interrupt service routine (ISR) to ensure that all valid interrupt sources are serviced. Table 126. IRQ/FIQ MMRs Bit Designations
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Description All interrupts OR'ed (FIQ only) Software interrupt Timer0 Timer1 Timer2 or wake-up timer Timer3 or watchdog timer Flash Control 0 Flash Control 1 ADC UART0 UART1 PLL lock I2C0 master IRQ I2C0 slave IRQ I2C1 master IRQ I2C1 slave IRQ SPI XIRQ0 (GPIO IRQ0 ) Comparator PSM XIRQ1 (GPIO IRQ1) PLA IRQ0 Comments This bit is set if any FIQ is active. User programmable interrupt source. General-Purpose Timer 0. General-Purpose Timer 1. General-Purpose Timer 2 or wake-up timer. General-Purpose Timer 3 or watchdog timer. Flash controller for Block 0 interrupt. Flash controller for Block 1 interrupt. ADC interrupt source bit. UART0 interrupt source bit. UART1 interrupt source bit. PLL lock bit. I2C master interrupt source bit. I2C slave interrupt source bit. I2C master interrupt source bit. I2C slave interrupt source bit. SPI interrupt source bit. External Interrupt 0. Voltage comparator source bit. Power supply monitor. External Interrupt 1. PLA Block 0 IRQ bit. Bit 22 23 24 25 Description XIRQ2 (GPIO IRQ2 ) XIRQ3 (GPIO IRQ3) PLA IRQ1 PWM Comments External Interrupt 2. External Interrupt 3. PLA Block 1 IRQ bit. PWM trip interrupt source bit.
IRQ
The IRQ is the exception signal to enter the IRQ mode of the processor. It services general-purpose interrupt handling of internal and external events. All 32 bits are logically OR'ed to create a single IRQ signal to the ARM7TDMI core. Descriptions of the four 32-bit registers dedicated to IRQ follow.
IRQSTA Register
IRQSTA is a read-only register that provides the current enabled IRQ source status (effectively a logic AND of the IRQSIG and IRQEN bits). When set to 1, that source generates an active IRQ request to the ARM7TDMI core. There is no priority encoder or interrupt vector generation. This function is implemented in software in a common interrupt handler routine.
IRQSTA Register
Name: Address: Default Value: Access: IRQSTA 0xFFFF0000 0x00000000 Read only
IRQSIG Register
IRQSIG reflects the status of the various IRQ sources. If a peripheral generates an IRQ signal, the corresponding bit in the IRQSIG is set; otherwise, it is cleared. The IRQSIG bits clear when the interrupt in the particular peripheral is cleared. All IRQ sources can be masked in the IRQEN MMR. IRQSIG is read only. This register should not be used in an interrupt service routine for determining the source of an IRQ exception; IRQSTA should only be used for this purpose.
IRQSIG Register
Name: Address: Default Value: Access: IRQSIG 0xFFFF0004 0x00000000 Read only
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ADuC7124
IRQEN Register
IRQEN provides the value of the current enable mask. When a bit is set to 1, the corresponding source request is enabled to create an IRQ exception. When a bit is set to 0, the corresponding source request is disabled or masked, which does not create an IRQ exception. The IRQEN register cannot be used to disable an interrupt. bit set to 1 in IRQEN clears, as a side effect, the same bit in FIQEN. An interrupt source can be disabled in both the IRQEN and FIQEN masks.
FIQSIG
FIQSIG reflects the status of the different FIQ sources. If a peripheral generates an FIQ signal, the corresponding bit in the FIQSIG is set; otherwise, it is cleared. The FIQSIG bits are cleared when the interrupt in the particular peripheral is cleared. All FIQ sources can be masked in the FIQEN MMR. FIQSIG is read only.
IRQEN Register
Name: Address: Default Value: Access: IRQEN 0xFFFF0008 0x00000000 Read/write
FIQSIG Register
Name: Address: Default Value: Access: FIQSIG 0xFFFF0104 0x00000000 Read only
IRQCLR Register
IRQCLR is a write-only register that allows the IRQEN register to clear to mask an interrupt source. Each bit that is set to 1 clears the corresponding bit in the IRQEN register without affecting the remaining bits. The pair of registers, IRQEN and IRQCLR, allow independent manipulation of the enable mask without requiring an atomic read-modify-write. This register should be used to disable an interrupt source only when: * * In the interrupt sources interrupt service routine. The peripheral is temporarily disabled by its own control register.
FIQEN
FIQEN provides the value of the current enable mask. When a bit is set to 1, the corresponding source request is enabled to create an FIQ exception. When a bit is set to 0, the corresponding source request is disabled or maskedm which does not create an FIQ exception. The FIQEN register cannot be used to disable an interrupt.
FIQEN Register
Name: Address: Default Value: Access: FIQEN 0xFFFF0108 0x00000000 Read/write
This register should not be used to disable an IRQ source if that IRQ source has an interrupt pending or could have an interrupt pending.
IRQCLR Register
Name: Address: Default Value: Access: IRQCLR 0xFFFF000C 0x00000000 Write only
FIQCLR
FIQCLR is a write-only register that allows the FIQEN register to clear to mask an interrupt source. Each bit that is set to 1 clears the corresponding bit in the FIQEN register without affecting the remaining bits. The pair of registers, FIQEN and FIQCLR, allows independent manipulation of the enable mask without requiring an atomic read-modify-write. This register should be used to disable an interrupt source only when: * * In the interrupt sources interrupt service routine. The peripheral is temporarily disabled by its own control register.
FAST INTERRUPT REQUEST (FIQ)
The fast interrupt request (FIQ) is the exception signal to enter the FIQ mode of the processor. It is provided to service data transfer or communication channel tasks with low latency. The FIQ interface is identical to the IRQ interface and provides the second level interrupt (highest priority). Four 32-bit registers are dedicated to FIQ: FIQSIG, FIQEN, FIQCLR, and FIQSTA. Bit 31 to Bit 1 of FIQSTA are logically OR'ed to create the FIQ signal to the core and to Bit 0 of both the FIQ and IRQ registers (FIQ source). The logic for FIQEN and FIQCLR does not allow an interrupt source to be enabled in both IRQ and FIQ masks. A bit set to 1 in FIQEN clears, as a side effect, the same bit in IRQEN. Likewise, a
This register should not be used to disable an IRQ source if that IRQ source has an interrupt pending or could have an interrupt pending.
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FIQCLR Register
Name: Address: Default Value: Access: FIQCLR 0xFFFF010C 0x00000000 Write only
PROGRAMMABLE PRIORITY PER INTERRUT (IRQP0/IRQP1/IRQP2/IRQP3)
IRQ_SOURCE FIQ_SOURCE
INTERNAL ARBITER LOGIC
POINTER FUNCTION (IRQVEC)
INTERRUPT VECTOR
FIQSTA
FIQSTA is a read-only register that provides the current enabled FIQ source status (effectively a logic AND of the FIQSIG and FIQEN bits). When set to 1, that source generates an active FIQ request to the ARM7TDMI core. There is no priority encoder or interrupt vector generation. This function is implemented in software in a common interrupt handler routine.
09123-054
BITS[31:23] UNUSED
BITS[22:7] (IRQBASE)
BITS[6:2] HIGHEST PRIORITY ACTIVE IRQ
BITS[1:0] LSBs
Figure 51. Interrupt Structure
VECTORED INTERRUPT CONTROLLER (VIC)
The ADUC7124 incorporates an enhanced interrupt control system or (vectored interrupt controller). The vectored interrupt controller for IRQ interrupt sources is enabled by setting Bit 0 of the IRQCONN register. Similarly, Bit 1 of IRQCONN enables the vectored interrupt controller for the FIQ interrupt sources. The vectored interrupt controller provides the following enhancements to the standard IRQ/FIQ interrupts: * Vectored interrupts--allows a user to define separate interrupt service routine addresses for every interrupt source. This is achieved by using the IRQBASE and IRQVEC registers. IRQ/FIQ interrupts--can be nested up to eight levels depending on the priority settings. An FIQ still has a higher priority than an IRQ. Therefore, if the VIC is enabled for both the FIQ and IRQ and prioritization is maximized, it is possible to have 16 separate interrupt levels. Programmable interrupt priorities--using the IRQP0 to IRQP3 registers, an interrupt source can be assigned an interrupt priority level value between 0 and 7.
FIQSTA Register
Name: Address: Default Value: Access: FIQSTA 0xFFFF0100 0x00000000 Read only
Programmed Interrupts
Because the programmed interrupts are not maskable, they are controlled by another register (SWICFG) that writes into the IRQSTA and IRQSIG registers and/or the FIQSTA and FIQSIG registers at the same time. The 32-bit register dedicated to software interrupt is SWICFG (described in Table 127). This MMR allows control of a programmed source interrupt. Table 127. SWICFG MMR Bit Designations
Bit 31:3 2 Description Reserved. Programmed interrupt FIQ. Setting/clearing this bit corresponds to setting/clearing Bit 1 of FIQSTA and FIQSIG. Programmed interrupt IRQ. Setting/clearing this bit corresponds to setting/clearing Bit 1 of IRQSTA and IRQSIG. Reserved.
*
*
VIC MMRs
IRQBASE Register The vector base register, IRQBASE, is used to point to the start address of memory used to store 32 pointer addresses. These pointer addresses are the addresses of the individual interrupt service routines. Name: Address: Default Value: Access: IRQBASE 0xFFFF0014 0x00000000 Read/write
1
0
Any interrupt signal must be active for at least the minimum interrupt latency time to be detected by the interrupt controller and to be detected by the user in the IRQSTA/FIQSTA register.
Table 128. IRQBASE MMR Bit Designations
Bit 31:16 15:0
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Type Read only R/W
Initial Value Reserved 0
Description Always read as 0. Vector base address.
ADuC7124
IRQVEC Register
The IRQ interrupt vector register, IRQVEC points to a memory address containing a pointer to the interrupt service routine of the currently active IRQ. This register should only be read when an IRQ occurs and IRQ interrupt nesting has been enabled by setting Bit 0 of the IRQCONN register. Name: Address: Default Value: Access: IRQVEC 0xFFFF001C 0x00000000 Read only
Bit 18:16 15 14:12 11 10:8 7 6:4 3:0 Name T2PI Reserved T1PI Reserved T0PI Reserved SWINTP Reserved Description A priority level of 0 to 7 can be set for Timer2. Reserved bit. A priority level of 0 to 7 can be set for Timer1. Reserved bit. A priority level of 0 to 7 can be set for Timer0. Reserved bit. A priority level of 0 to 7 can be set for the software interrupt source. Interrupt 0 cannot be prioritized.
Table 129. IRQVEC MMR Bit Designations
Bit 31:23 22:7 6:2 Type Read only R/W Read only Initial Value 0 0 0 Description Always read as 0. IRQBASE register value. Highest priority source. This is a value between 0 and 27 representing the possible interrupt sources. For example, if the highest currently active IRQ is Timer 2, then these bits are [00100]. Reserved bits.
IRQP1 Register
Name: Address: Default Value: Access: IRQP1 0xFFFF0024 0x00000000 Read/write
Table 131. IRQP1 MMR Bit Designations
Bit 31 30:28 27 26:24 23 22:20 19 18:16 15 14:12 11 10:8 7 6:4 5 2:0 Name Reserved I2C1SPI Reserved I2C1MPI Reserved I2C0SPI Reserved I2C0MPI Reserved PLLPI Reserved UART1PI Reserved UART0PI Reserved ADCPI Description Reserved bit. A priority level of 0 to 7 can be set for the I2C1 slave. Reserved bit. A priority level of 0 to 7 can be set for the I2C1 master. Reserved bit. A priority level of 0 to 7 can be set for the I2C0 slave. Reserved bit. A priority level of 0 to 7 can be set for the I2C 0 master. Reserved bit. A priority level of 0 to 7 can be set for the PLL lock interrupt. Reserved bit. A priority level of 0 to 7 can be set for UART1. Reserved bit. A priority level of 0 to 7 can be set for UART0. Reserved bit. A priority level of 0 to 7 can be set for the ADC interrupt source.
1:0
Reserved
0
Priority Registers
The IRQ interrupt vector register, IRQVEC points to a memory address containing a pointer to the interrupt service routine of the currently active IRQ. This register should only be read when an IRQ occurs and IRQ interrupt nesting has been enabled by setting Bit 0 of the IRQCONN register.
IRQP0 Register
Name: Address: Default Value: Access: IRQP0 0xFFFF0020 0x00000000 Read/write
Table 130. IRQP0 MMR Bit Designations
Bit 31 30:28 27 26:24 23 22:20 19 Name Reserved Flash1PI Reserved Flash0PI Reserved T3PI Reserved Description Reserved bit. A priority level of 0 to 7 can be set for the Flash Block 1 controller interrupt source. Reserved bit. A priority level of 0 to 7 can be set for the Flash Block 0 controller interrupt source. Reserved bit. A priority level of 0 to 7 can be set for Timer 3. Reserved bit.
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IRQP2 Register
Name: Address: Default Value: Access: IRQP2 0xFFFF0028 0x00000000 Read/write interrupt source priority level. In this default state, an FIQ does have a higher priority than an IRQ. Name: Address: Default Value: Access: IRQCONN 0xFFFF0030 0x00000000 Read/write
Table 132. IRQP2 MMR Bit Designations
Bit 31 30:28 27 26:24 23 22:20 19 18:16 15 14:12 11 10:8 7 6:4 3 2:0 Name Reserved IRQ3PI Reserved IRQ2PI Reserved PLA0PI Reserved IRQ1PI Reserved PSMPI Reserved COMPI Reserved IRQ0PI Reserved SPIPI Description Reserved bit. A priority level of 0 to 7 can be set for IRQ3. Reserved bit. A priority level of 0 to 7 can be set for IRQ2. Reserved bit. A priority level of 0 to 7 can be set for PLA IRQ0. Reserved bit. A priority level of 0 to 7 can be set for IRQ1. Reserved bit. A priority level of 0 to 7 can be set for the power supply monitor interrupt source. Reserved bit. A priority level of 0 to 7 can be set for the comparator. Reserved bit. A priority level of 0 to 7 can be set for IRQ0. Reserved bit. A priority level of 0 to 7 can be set for SPI.
Table 134. IRQCONN MMR Bit Designations
Bit 31:2 1 Name Reserved ENFIQN Description These bits are reserved and should not be written to. Setting this bit to 1 enables nesting of FIQ interrupts. Clearing this bit means no nesting or prioritization of FIQs is allowed. Setting this bit to 1 enables nesting of IRQ interrupts. Clearing this bit means no nesting or prioritization of IRQs is allowed.
0
ENIRQN
IRQSTAN Register
If IRQCONN.0 is asserted and IRQVEC is read, one of these bits is asserted. The bit that asserts depends on the priority of the IRQ. If the IRQ is of Priority 0, then Bit 0 asserts, if Priority 1, then Bit 1 asserts, and so on. When a bit is set in this register, all interrupts of that priority and lower are blocked. To clear a bit in this register, all bits of a higher priority must be cleared first. It is only possible to clear one bit at a time. For example, if this register is set to 0x09, writing 0xFF changes the register to 0x08, and writing 0xFF a second time changes the register to 0x00. Name: Address: Default Value: Access: IRQSTAN 0xFFFF003C 0x00000000 Read/write
IRQP3 Register
Name: Address: Default Value: Access: IRQP3 0xFFFF002C 0x00000000 Read/write
Table 133. IRQP3 MMR Bit Designations
Bit 31:7 6:4 3 2:0 Name Reserved PWMPI Reserved PLA1PI Description Reserved bit. A priority level of 0 to 7 can be set for PWM. Reserved bit. A priority level of 0 to 7 can be set for PLA IRQ1.
Table 135. IRQSTAN MMR Bit Designations
Bit 31:8 7:0 Name Reserved Description These bits are reserved and should not be written to. Setting this bit to 1 enables nesting of FIQ interrupts. Clearing this bit, means no nesting or prioritization of FIQs is allowed.
IRQCONN Register
The IRQCONN register is the IRQ and FIQ control register. It contains two active bits: the first to enable nesting and prioritization of IRQ interrupts and the other to enable nesting and prioritization of FIQ interrupts. If these bits are cleared, FIQs and IRQs can still be used, but it is not possible to nest IRQs or FIQs, nor is it possible to set an
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FIQVEC Register
The FIQ interrupt vector register, FIQVEC, points to a memory address containing a pointer to the interrupt service routine of the currently active FIQ. This register should be read only when an FIQ occurs and FIQ interrupt nesting has been enabled by setting Bit 1 of the IRQCONN register. Name: Address: Default Value: Access: FIQVEC 0xFFFF011C 0x00000000 Read only the register to 0x08 and writing 0xFF a second time changes the register to 0x00. Name: Address: Default Value: Access: FIQSTAN 0xFFFF013C 0x00000000 Read/write
Table 137. FIQSTAN MMR Bit Designations
Bit 31:8 7:0 Name Reserved Description These bits are reserved and should not be written to. Setting this bit to 1 enables nesting of FIQ interrupts. Clearing this bit, means no nesting or prioritization of FIQs is allowed.
Table 136. FIQVEC MMR Bit Designations
Bit 31:23 22:7 6:2 Type Read only R/W Initial Value 0 0 0 Description Always read as 0. IRQBASE register value. Highest priority source. This is a value between 0 and 27, representing the currently active interrupt source. The interrupts are listed in Table 126. For example, if the highest currently active FIQ is Timer2, then these bits are [00100]. Reserved bits.
External Interrupts and PLA interrupts
The ADuC7124 provides up to four external interrupt sources and two PLA interrupt sources. These external interrupts can be individually configured as level or rising/falling edge triggered. To enable the external interrupt source or the PLA interrupt source, first, the appropriate bit must be set in the FIQEN or IRQEN register. To select the required edge or level to trigger on, the IRQCONE register must be appropriately configured. To properly clear an edge-based external IRQ interrupt or an edge-based PLA interrupt, set the appropriate bit in the IRQCLRE register. IRQCONE Register Name: Address: Default Value: Access: IRQCONE 0xFFFF0034 0x00000000 Read/write
1:0
Reserved
0
FIQSTAN Register
If IRQCONN.1 is asserted and FIQVEC is read, one of these bits assert. The bit that asserts depends on the priority of the FIQ. If the FIQ is of Priority 0, Bit 0 asserts, if Priority 1, Bit 1 asserts, and so forth. When a bit is set in this register all interrupts of that priority and lower are blocked. To clear a bit in this register, all bits of a higher priority must be cleared first. It is possible to clear only one bit at a time. For example, if this register is set to 0x09, then writing 0xFF changes Table 138. IRQCONE MMR Bit Designations
Bit 31:12 11:10 Value 11 10 01 00 11 10 01 00 Name Reserved PLA1SRC[1:0]
9:8
IRQ3SRC[1:0]
Description These bits are reserved and should not be written to. PLA IRQ1 triggers on falling edge. PLA IRQ1 triggers on rising edge. PLA IRQ1 triggers on low level. PLA IRQ1 triggers on high level. External IRQ3 triggers on falling edge. External IRQ3 triggers on rising edge. External IRQ3 triggers on low level. External IRQ3 triggers on high level.
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Bit 7:6 Value 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 Name IRQ2SRC[1:0] Description External IRQ2 triggers on falling edge. External IRQ2 triggers on rising edge. External IRQ2 triggers on low level. External IRQ2 triggers on high level. PLA IRQ0 triggers on falling edge. PLA IRQ0 triggers on rising edge. PLA IRQ0 triggers on low level. PLA IRQ0 triggers on high level. External IRQ1 triggers on falling edge. External IRQ1 triggers on rising edge. External IRQ1 triggers on low level. External IRQ1 triggers on high level. External IRQ0 triggers on falling edge. External IRQ0 triggers on rising edge. External IRQ0 triggers on low level. External IRQ0 triggers on high level.
5:4
PLA0SRC[1:0]
3:2
IRQ1SRC[1:0]
1:0
IRQ0SRC[1:0]
IRQCLRE Register
Name: Address: Default Value: Access: IRQCLRE 0xFFFF0038 0x00000000 Read/write
Table 139. IRQCLRE MMR Bit Designations
Bit 31:25 24 23 22 21 20 19:18 17 16:0 Name Reserved PLA1CLRI IRQ3CLRI IRQ2CLRI PLA0CLRI IRQ1CLRI Reserved IRQ0CLRI Reserved Description These bits are reserved and should not be written to. A 1 must be written to this bit in the PLA IRQ1 interrupt service routine to clear an edgetriggered PLA IRQ1 interrupt. A 1 must be written to this bit in the external IRQ3 interrupt service routine to clear an edgetriggered IRQ3 interrupt. A 1 must be written to this bit in the external IRQ2 interrupt service routine to clear an edgetriggered IRQ2 interrupt. A 1 must be written to this bit in the PLA IRQ0 interrupt service routine to clear an edgetriggered PLA IRQ0 interrupt. A 1 must be written to this bit in the external IRQ1 interrupt service routine to clear an edgetriggered IRQ1 interrupt. These bits are reserved and should not be written to. A 1 must be written to this bit in the external IRQ0 interrupt service routine to clear an edge triggered IRQ0 interrupt. These bits are reserved and should not be written to.
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TIMERS
The ADuC7124 has four general-purpose timer/counters. * * * * Timer0 Timer1 Timer2 or wake-up timer Timer3 or watchdog timer
32.768kHz OSCILLATOR UCLK HCLK TIMER0 VALUE PRESCALER /1, 16, OR 256
Timer0 (RTOS Timer)
Timer0 is a general-purpose, 16-bit timer (count down) with a programmable prescaler. The prescaler source is the core clock frequency (HCLK) and can be scaled by factors of 1, 16, or 256. Timer0 can be used to start ADC conversions as shown in the block diagram in Figure 52.
16-BIT LOAD
These four timers in their normal mode of operation can be either free running or periodic. In free-running mode, the counter decreases from the maximum value until zero scale is reached and starts again at the minimum value. It also increases from the minimum value until full scale is reached and starts again at the maximum value. In periodic mode, the counter decrements/increments from the value in the load register (TxLD MMR) until zero/full scale is reached and starts again at the value stored in the load register. The timer interval is calculated as follows:
16-BIT DOWN COUNTER
TIMER0 IRQ ADC CONVERSION
09123-036
Figure 52. Timer0 Block Diagram
The Timer0 interface consists of four MMRs: T0LD, T0VAL, T0CON, and T0CLRI.
T0LD Register
Name: Address: Default Value: Access: T0LD 0xFFFF0300 0x0000 Read/write
Interval =
(TxD ) x Prescaler
Source Clock
The value of a counter can be read at any time by accessing its value register (TxVAL). Note that, when a timer is being clocked from a clock other than a core clock, an incorrect value may be read (due to asynchronous clock system). In this configuration, TxVAL should always be read twice. If the two readings are different, it should be read a third time to get the correct value. Timers are started by writing in the control register of the corresponding timer (TxCON). In normal mode, an IRQ is generated each time the value of the counter reaches zero when counting down. It is also generated each time the counter value reaches full scale when counting up. An IRQ can be cleared by writing any value to clear the register of that particular timer (TxCLRI). When using an asynchronous clock-to-clock timer, the interrupt in the timer block can take more time to clear than the time it takes for the code in the interrupt routine to execute. Ensure that the interrupt signal is cleared before leaving the interrupt service routine. This can be done by checking the IRQSTA MMR.
T0LD is a 16-bit load register.
T0VAL Register
Name: Address: Default Value: Access: T0VAL 0xFFFF0304 0xFFFF Read
T0VAL is a 16-bit read-only register representing the current state of the counter.
T0CON Register
Name: Address: Default Value: Access: T0CON 0xFFFF0308 0x0000 Read/write
T0CON is the configuration MMR described in Table 140.
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Table 140. T0CON MMR Bit Descriptions
Bit 31:8 7 Value Description Reserved. Timer0 enable bit. Set by the user to enable Timer0. Cleared by the user to disable Timer0 by default. Timer0 mode. Set by the user to operate in periodic mode. Cleared by the user to operate in free-running mode. Default mode. Clock select bits. HCLK. UCLK. 32.768 kHz. Reserved. Prescale. Core clock/1. Default value. Core clock/16. Core clock/256. Undefined. Equivalent to 00. Reserved.
32kHz OSCILLATOR HCLK UCLK P1.1 PRESCALER /1, 16, 256, OR 32,768 32-BIT LOAD 32-BIT UP/DOWN COUNTER
TIMER1 IRQ ADC CONVERSION TIMER1 VALUE
IRQ[19:0]
CAPTURE
6
Figure 53. Timer1 Block Diagram
5:4 00 01 10 11 3:2 00 01 10 11 1:0
The Timer1 interface consists of five MMRs: T1LD, T1VAL, T1CON, T1CLRI, and T1CAP.
T1LD Register
Name: Address: Default Value: Access: T1LD 0xFFFF0320 0x00000000 Read/write
T1LD is a 32-bit load register.
T0CLRI Register
Name: Address: Default Value: Access: T0CLRI 0xFFFF030C 0xFF Write only
T1VAL Register
Name: Address: Default Value: Access: T1VAL 0xFFFF0324 0xFFFFFFFF Read only
T0CLRI is an 8-bit register. Writing any value to this register clears the interrupt.
T1VAL is a 32-bit read-only register that represents the current state of the counter.
Timer1 (General-Purpose Timer)
Timer1 is a general-purpose, 32-bit timer (count down or count up) with a programmable prescaler. The source can be the 32 kHz external crystal, the undivided system, the core clock, or P1.1 (maximum frequency 41.78 MHz). This source can be scaled by a factor of 1, 16, 256, or 32,768. The counter can be formatted as a standard 32-bit value or as hours: minutes: seconds: hundredths. Timer1 has a capture register (T1CAP) that can be triggered by a selected IRQ source initial assertion. This feature can be used to determine the assertion of an event more accurately than the precision allowed by the RTOS timer when the IRQ is serviced. Timer1 can be used to start ADC conversions.
T1CON Register
Name: Address: Default Value: Access: T1CON 0xFFFF0328 0x0000 Read/write
T1CON is the configuration MMR described in Table 141.
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ADuC7124
Table 141. T1CON MMR Bit Descriptions
Bit 31:18 17 Value Description Reserved. Event select bit. Set by the user to enable time capture of an event. Cleared by the user to disable time capture of an event. Event select range, 0 to 31. These events are as described in Table 126. All events are offset by two, that is, Event 2 in Table 126 becomes Event 0 for the purposes of Timer1. Clock select. Core clock (41 MHz/2CD). 32.768 kHz. UCLK. P1.0 raising edge triggered. Count up. Set by the user for Timer1 to count up. Cleared by the user for Timer1 to count down by default. Timer1 enable bit. Set by the user to enable Timer1. Cleared by the user to disable Timer1 by default. Timer1 mode. Set by the user to operate in periodic mode. Cleared by the user to operate in free-running mode. Default mode. Format. Binary. Reserved. Hr: min: sec: hundredths (23 hours to 0 hour). Hr: min: sec: hundredths (255 hours to 0 hour). Prescale. Source clock/1. Source clock/16. Source clock/256. Source clock/32,768.
T1CAP is a 32-bit register. It holds the value contained in T1VAL when a particular event occurrs. This event must be selected in T1CON.
Timer2 (Wake-Up Timer)
Timer2 is a 32-bit wake-up timer, count down or count up, with a programmable prescaler. The prescaler is clocked directly from one of four clock sources, including the core clock (default selection), the internal 32.768 kHz oscillator, the external 32.768 kHz watch crystal, or the PLL undivided clock. The selected clock source can be scaled by a factor of 1, 16, 256, or 32,768. The wake-up timer continues to run when the core clock is disabled. This gives a minimum resolution of 22 ns when the core is operating at 41.78 MHz and with a prescaler of 1. Capture of the current timer value is enabled if the Timer2 interrupt is enabled via IRQEN[4] (see Table 126). The counter can be formatted as a plain 32-bit value or as hours: minutes: seconds: hundredths. Timer2 reloads the value from T2LD either when Timer2 overflows or immediately when T2ICLR is written. The Timer2 interface consists of four MMRs, shown in Table 142. Table 142. Timer2 Interface Registers
Register T2LD T2VAL T2CLRI T2CON Description 32-bit register. Holds 32-bit unsigned integers. 32-bit register. Holds 32-bit unsigned integers. This register is read only. 8-bit register. Writing any value to this register clears the Timer2 interrupt. Configuration MMR.
16:12
11:9 000 001 010 011 8
7
6
5:4 00 01 10 11 3:0 0000 0100 1000 1111
Timer2 Load Registers
Name: Address: Default Value: Access: T2LD 0xFFFF0340 0x00000 Read/write
T1CLRI Register
Name: Address: Default Value: Access: T1CLRI 0xFFFF032C 0xFF Read/write
T2LD is a 32-bit register, which holds the 32-bit value that is loaded into the counter.
Timer2 Clear Register
Name: Address: Default Value: Access: T2CLRI 0xFFFF034C 0x00 Write only
T1CLRI is an 8-bit register. Writing any value to this register clears the Timer1 interrupt.
T1CAP Register
Name: Address: Default Value: Access: T1CAP 0xFFFF0330 0x00000000 Read only
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This 8-bit write-only MMR is written (with any value) by user code to refresh (reload) Timer2. T2VAL is a 32-bit register that holds the current value of Timer2.
Timer2 Control Register
Name: Address: Default Value: Access: T2CON 0xFFFF0348 0x0000 Read/write
Timer2 Value Register
Name: Address: Default Value: Access: T2VAL 0xFFFF0344 0x0000 Read only
This 32-bit MMR configures the mode of operation for Timer2.
Table 143. T2CON MMR Bit Designations
Bit 31:11 10:9 Value Description Reserved. Clock source select. External 32.768 kHz watch crystal (default). External 32.768 kHz watch crystal. Internal 32.768 kHz oscillator. HCLK. Count up. Set by the user for Timer2 to count up. Cleared by the user for Timer2 to count down (default). Timer2 enable bit. Set by the user to enable Timer2. Cleared by the user to disable Timer2 (default). Timer2 mode. Set by the user to operate in periodic mode. Cleared by the user to operate in free-running mode (default). Format. Binary (default). Reserved. Hr: min: sec: hundredths (23 hours to 0 hours). Hr: min: sec: hundredths (255 hours to 0 hours). Prescaler. Source clock/1 (default). Source clock/16. Source clock/256. This setting should be used in conjunction with Timer2 Format 10 and Format 11. Source clock/32,768.
00 01 10 11 8
7
6
5:4 00 01 10 11 3:0 0000 0100 1000 1111
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ADuC7124
Timer3 (Watchdog Time)
Timer3 has two modes of operation: normal mode and watchdog mode. The watchdog timer is used to recover from an illegal software state. Once enabled, it requires periodic servicing to prevent it from forcing a processor reset.
T3VAL Register
Name: Address: Default Value: Access: T3VAL 0xFFFF0364 0xFFFF Read only
Normal Mode
Timer3 in normal mode is identical to Timer0, except for the clock source and the count-up functionality. The clock source is 32 kHz from the PLL and can be scaled by a factor of 1, 16, or 256 (see Figure 54).
16-BIT LOAD WATCHDOG RESET TIMER3 IRQ
09123-037
T3VAL is a 16-bit read-only register that represents the current state of the counter.
T3CON Register
Name: Address: Default Value: Access: T3CON 0xFFFF0368 0x0000 Read/write
32.768kHz
PRESCALER / 1, 16 OR 256
16-BIT UP/DOWN COUNTER
TIMER3 VALUE
Figure 54. Timer3 Block Diagram
T3CON is the configuration MMR described in Table 144. Table 144. T3CON MMR Bit Descriptions
Bit 31:9 8 Value Description Reserved. Count up. Set by the user for Timer3 to count up. Cleared by the user for Timer3 to count down by default. Timer3 enable bit. Set by the user to enable Timer3. Cleared by the user to disable Timer3 by default. Timer3 mode. Set by the user to operate in periodic mode. Cleared by the user to operate in free-running mode (default mode). Watchdog mode enable bit. Set by the user to enable watchdog mode. Cleared by the user to disable watchdog mode by default. Secure clear bit. Set by the user to use the secure clear option. Cleared by the user to disable the secure clear option by default. Prescale. Source clock/1 by default. Source clock/16. Source clock/256. Undefined. Equivalent to 00. Watchdog IRQ option bit. Set by the user to produce an IRQ instead of a reset when the watchdog reaches 0. Cleared by the user to disable the IRQ option. Reserved.
Watchdog Mode
Watchdog mode is entered by setting Bit 5 in the T3CON MMR. Timer3 decreases from the value present in the T3LD register until 0 is reached. T3LD is used as the timeout. The maximum timeout can be 512 sec using the prescaler/256 and full-scale in T3LD. Timer3 is clocked by the internal 32 kHz crystal when operating in the watchdog mode. Note that, to enter watchdog mode successfully, Bit 5 in the T3CON MMR must be set after writing to the T3LD MMR. If the timer reaches 0, a reset or an interrupt occurs, depending on Bit 1 in the T3CON register. To avoid reset or interrupt, any value must be written to T3CLRI before the expiration period. This reloads the counter with T3LD and begins a new timeout period. When watchdog mode is entered, T3LD and T3CON are writeprotected. These two registers cannot be modified until a reset clears the watchdog enable bit, which causes Timer3 to exit watchdog mode. The Timer3 interface consists of four MMRs: T3LD, T3VAL, T3CON, and T3CLRI.
7
6
5
4
T3LD Register
Name: Address: Default Value: Access: T3LD 0xFFFF0360 0x0000 Read/write
3:2 00 01 10 11 1
T3LD is a 16-bit load register.
0
Rev. 0 | Page 88 of 96
ADuC7124
T3CLRI Register
Name: Address: Default Value: Access: T3CLRI 0xFFFF036C 0x00 Write only The initial value or seed is written to T3CLRI before entering watchdog mode. After entering watchdog mode, a write to T3CLRI must match this expected value. If it matches, the LFSR is advanced to the next state when the counter reload occurs. If it fails to match the expected state, a reset is immediately generated, even if the count has not yet expired. The value 0x00 should not be used as an initial seed due to the properties of the polynomial. The value 0x00 is always guaranteed to force an immediate reset. The value of the LFSR cannot be read; it must be tracked/generated in software. Example of a sequence: 1. 2. 3. 4. 5. Enter initial seed, 0xAA, in T3CLRI before starting Timer3 in watchdog mode. Enter 0xAA in T3CLRI; Timer3 is reloaded. Enter 0x37 in T3CLRI; Timer3 is reloaded. Enter 0x6E in T3CLRI; Timer3 is reloaded. Enter 0x66. 0xDC was expected; the watchdog resets the chip.
T3CLRI is an 8-bit register. Writing any value to this register on successive occassions clears the Timer3 interrupt in normal mode or resets a new timeout period in watchdog mode. Note that the user must perform successive writes to this register to ensure resetting the timeout period.
Secure Clear Bit (Watchdog Mode Only)
The secure clear bit is provided for a higher level of protection. When set, a specific sequential value must be written to T3CLRI to avoid a watchdog reset. The value is a sequence generated by the 8-bit linear feedback shift register (LFSR) polynomial = X8 + X6 + X5 + X + 1, as shown in Figure 55.
Q 7 CLOCK D Q 6 D Q 5 D Q 4 D Q 3 D Q 2 D Q 1 D Q 0 D
09123-038
Figure 55. 8-Bit LFSR
Rev. 0 | Page 89 of 96
ADuC7124 HARDWARE DESIGN CONSIDERATIONS
POWER SUPPLIES
The ADuC7124 operational power supply voltage range is 2.7 V to 3.6 V. Separate analog and digital power supply pins (AVDD and IOVDD, respectively) allow AVDD to be kept relatively free of noisy digital signals often present on the system IOVDD line. In this mode, the part can also operate with split supplies; that is, it can use different voltage levels for each supply. For example, the system can be designed to operate with an IOVDD voltage level of 3.3 V while the AVDD level can be at 3 V or vice versa. A typical split supply configuration is shown in Figure 56.
DIGITAL SUPPLY + - 10F ANALOG SUPPLY + -
Finally, note that the analog and digital ground pins on the ADuC7124 must be referenced to the same system ground reference point at all times.
IOVDD Supply Sensitivity
The IOVDD supply is sensitive to high frequency noise because it is the supply source for the internal oscillator and PLL circuits. When the internal PLL loses lock, the clock source is removed by a gating circuit from the CPU, and the ARM7TDMI core stops executing code until the PLL regains lock. This feature ensures that no flash interface timings or ARM7TDMI timings are violated. Typically, frequency noise greater than 50 kHz and 50 mV p-p on top of the supply causes the core to stop working. If decoupling values recommended in the Power Supplies section do not sufficiently dampen all noise sources below 50 mV on IOVDD, a filter such as the one shown in Figure 58 is recommended.
1H
ADuC7124
AVDD IOVDD DACV DD
10F
0.1F GNDREF DACGND AGND
0.1F
09123-044
IOGND
DIGITAL + SUPPLY -
10F
ADuC7124
IOVDD
Figure 56. External Dual Supply Connections
As an alternative to providing two separate power supplies, the user can reduce noise on AVDD by placing a small series resistor and/or ferrite bead between AVDD and IOVDD and then decoupling AVDD separately to ground. An example of this configuration is shown in Figure 57. With this configuration, other analog circuitry (such as op amps, voltage reference, or any other analog circuitry) can be powered from the AVDD supply line as well.
DIGITAL SUPPLY 10F BEAD ANALOG SUPPLY
0.1F
0.1F
Figure 58. Recommended IOVDD Supply Filter
Linear Voltage Regulator
The ADuC7124 requires a single 3.3 V supply, but the core logic requires a 2.6 V supply. An on-chip linear regulator generates the 2.6 V from IOVDD for the core logic. The LVDD pin is the 2.6 V supply for the core logic. An external compensation capacitor of 0.47 F must be connected between LVDD and DGND (as close as possible to these pins) to act as a tank of charge as shown in Figure 59.
ADuC7124
+ -
ADuC7124
DVDD DVDD AVDD
10F
0.1F
0.1F
DVDD DGND
09123-145
DGND DGND
AGND
LVDD 0.47F DGND
Figure 57. External Single Supply Connections
Notice that in both Figure 56 and Figure 57, a large value (10 F) reservoir capacitor sits on IOVDD, and a separate 10 F capacitor sits on AVDD. In addition, local small-value (0.1 F) capacitors are located at each AVDD and IOVDD pin of the chip. As per standard design practice, be sure to include all of these capacitors and ensure that the smaller capacitors are close to each AVDD pin with trace lengths as short as possible. Connect the ground terminal of each of these capacitors directly to the underlying ground plane.
Figure 59. Voltage Regulator Connections
The LVDD pin should not be used for any other chip. It is also recommended to use excellent power supply decoupling on IOVDD to help improve line regulation performance of the onchip voltage regulator.
Rev. 0 | Page 90 of 96
09123-046
09123-087
IOGND
ADuC7124
GROUNDING AND BOARD LAYOUT RECOMMENDATIONS
As with all high resolution data converters, special attention must be paid to grounding and PC board layout of the ADuC7124-based designs to achieve optimum performance from the ADCs and DAC. Although the part has separate pins for analog and digital ground (AGND and IOGND), the user must not tie these to two separate ground planes unless the two ground planes are connected very close to the part. This is illustrated in the simplified example shown in Figure 60a. In systems where digital and analog ground planes are connected together somewhere else (at the power supply of the system, for example), the planes cannot be reconnected near the part because a ground loop results. In these cases, tie all the ADuC7124 AGND and IOGND pins to the analog ground plane, as illustrated in Figure 60b. In systems with only one ground plane, ensure that the digital and analog components are physically separated onto separate halves of the board so that digital return currents do not flow near analog circuitry (and vice versa). The ADuC7124 can then be placed between the digital and analog sections, as illustrated in Figure 60c. For example, do not power components on the analog side (as seen in Figure 60b) with IOVDD because that forces return currents from IOVDD to flow through AGND. Avoid digital currents flowing under analog circuitry, which can occur if a noisy digital chip is placed on the left half of the board (shown in Figure 60c). If possible, avoid large discontinuities in the ground plane(s), such as those formed by a long trace on the same layer, because they force return signals to travel a longer path. In addition, make all connections to the ground plane directly, with little or no trace separating the pin from its via to ground. When connecting fast logic signals (rise/fall time < 5 ns) to any of the ADuC7124 digital inputs, add a series resistor to each relevant line to keep rise and fall times longer than 5 ns at the input pins of the part. A value of 100 or 200 is usually sufficient to prevent high speed signals from coupling capacitively into the part and affecting the accuracy of ADC conversions.
CLOCK OSCILLATOR
The clock source for the ADuC7124 can be generated by the internal PLL or by an external clock input. To use the internal PLL, connect a 32.768 kHz parallel resonant crystal between XCLKI and XCLKO, and connect a capacitor from each pin to ground as shown in Figure 61. The crystal allows the PLL to lock correctly to give a frequency of 41.78 MHz. If no external crystal is present, the internal oscillator is used to give a typical frequency of 32.768 kHz 3%.
ADuC7124
XCLKI 12pF 32.768kHz
09123-048
a.
PLACE ANALOG COMPONENTS HERE
PLACE DIGITAL COMPONENTS HERE
AGND
DGND
12pF
XCLKO
TO INTERNAL PLL
b.
PLACE ANALOG COMPONENTS HERE AGND
PLACE DIGITAL COMPONENTS HERE
Figure 61. External Parallel Resonant Crystal Connections
DGND
To use an external source clock input instead of the PLL (see Figure 62), Bit 1 and Bit 0 of PLLCON must be modified.The external clock uses P0.7 and XCLK.
ADuC7124
XCLKO XCLKI
c.
PLACE ANALOG COMPONENTS HERE
PLACE DIGITAL COMPONENTS HERE
XCLK
DGND
09123-047
Figure 62. Connecting an External Clock Source
Figure 60. System Grounding Schemes
In all of these scenarios, and in more complicated real-life applications, the users should pay particular attention to the flow of current from the supplies and back to ground. Make sure the return paths for all currents are as close as possible to the paths the currents took to reach their destinations.
Using an external clock source, the ADuC7124 specified operational clock speed range is 50 kHz to 41.78 MHz 1%, which ensures correct operation of the analog peripherals and Flash/EE.
Rev. 0 | Page 91 of 96
09123-049
EXTERNAL CLOCK SOURCE
TO FREQUENCY DIVIDER
ADuC7124
POWER-ON RESET OPERATION
An internal power-on reset (POR) is implemented on the ADuC7124. For LVDD below 2.40 V typical, the internal POR holds the part in reset. As LVDD rises above 2.40 V, an internal timer times out for typically 128 ms before the part is released from reset. The user must ensure that the power supply, IOVDD, reaches a stable 2.7 V minimum level by this time. Likewise, on power-down, the internal POR holds the part in reset until LVDD drops below 2.40 V. Figure 63 illustrates the operation of the internal POR in detail.
RST IOVDD 2.6V 3.3V
2.40V TYP LVDD 164ms TYP
2.40V TYP
POR 0.12ms TYP
09123-050
Figure 63. Internal Power-On Reset Operation
Rev. 0 | Page 92 of 96
ADuC7124 OUTLINE DIMENSIONS
9.00 BSC SQ 0.60 MAX 0.60 MAX
49 48
0.30 0.25 0.18
64 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
8.75 BSC SQ
EXPOSED PAD
(BOTTOM VIEW)
*4.85 4.70 SQ 4.55
0.50 0.40 0.30
33 32
16 17
1.00 0.85 0.80
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC 0.20 REF
7.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
082908-B
SEATING PLANE
*COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 EXCEPT FOR EXPOSED PAD DIMENSION
Figure 64. 64-Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm x 9 mm Body, Very Thin Quad (CP-64-1) Dimensions shown in millimeters
ORDERING GUIDE
Model1 ADuC7124BCPZ126 ADuC7124BCPZ126-RL EVAL-ADUC7124QSPZ ADC Channels 10 10 DAC Channels 2 2 Flash/Ram 126 kB/32 kB 126 kB/32 kB GPIO 30 30 Downloader UART UART Temperature Range -40C to +125C -40C to +125C Package Description 64-Lead LFCSP_VQ 64-Lead LFCSP_VQ ADuC7124 QuickStart Development System Package Option CP-64-1 CP-64-1 Ordering Quantity 260 2500
1
Z = RoHS Compliant Part.
Rev. 0 | Page 93 of 96
ADuC7124 NOTES
Rev. 0 | Page 94 of 96
ADuC7124 NOTES
Rev. 0 | Page 95 of 96
ADuC7124 NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
(c)2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09123-0-7/10(0)
Rev. 0 | Page 96 of 96

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